LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 41

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
3.8
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100 µs.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_LOAD field is initialized to FFFFh. The GPT_CNT register is also
initialized to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any
time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in
the GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
General Purpose Timer (GP Timer)
END_SEL = 0
END_SEL = 1
Table 3.8 32-Bit Endian Ordering Logic Operation
Table 3.9 16-Bit Endian Ordering Logic Operation
END_SEL = 0
END_SEL = 1
END_SEL = 0
END_SEL = 1
D[31:24]
3
0
DATASHEET
D[23:16]
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
A1=1
A1=0
41
Host Data Bus
2
1
D[15:8]
D[15:8]
Host Data Bus
3
1
0
2
1
3
2
0
1
2
D[7:0]
D[7:0]
2
0
1
3
0
2
3
1
0
3
Revision 1.3 (02-23-10)