LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 50

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
MAC and Host
Internal Clock
Management
MAC Power
Interface
BLOCK
Device
PHY
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN89218 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host
is required to check the READY bit and verify that it is set before attempting any other reads or writes
of the device. Before the LAN89218 is fully awake from this state the EDPWRDOWN bit in register 17
of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit
until the READY bit is set. After clearing the EDPWRDOWN bit the LAN89218 is ready to resume
normal operation. At this time the WUPS field can be cleared.
(NORMAL OPERATION)
Full ON
Full ON
Full ON
Full ON
Table 3.11 Power Management States
D0
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
DATASHEET
RX Power Mgmt. Block
50
Full ON
Full ON
(WOL)
OFF
D1
On
Energy Detect Power-Down
(ENERGY DETECT)
OFF
OFF
OFF
D2
SMSC LAN89218
Datasheet