LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 103
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LAN89218AQ
Manufacturer Part Number
LAN89218AQ
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN89218AQ.pdf
(155 pages)
Specifications of LAN89218AQ
Lead Free Status / RoHS Status
Compliant
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
5.3.19
5.3.20
BITS
BITS
31:0
29:8
7:0
31
30
RX Dropped Frame Counter (RX_DFC). This counter is incremented every
time a receive frame is dropped. RX_DFC is cleared on any read of this
register.
An interrupt can be issued when this counter passes through its halfway
point (7FFFFFFFh to 80000000h).
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
R/nW. When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
Reserved.
CSR Address. The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
RX_DROP– Receiver Dropped Frames Counter
This register indicates the number of receive frames that have been dropped.
MAC_CSR_CMD – MAC CSR Synchronizer Command Register
This register is used to control the read and write operations with the MAC CSR’s.
Offset:
Offset:
DESCRIPTION
DESCRIPTION
A0h
A4h
DATASHEET
103
Size:
Size:
32 bits
32 bits
TYPE
TYPE
R/W
R/W
RC
SC
RO
Revision 1.3 (02-23-10)
00000000h
DEFAULT
DEFAULT
00h
0
0
-
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