LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 43

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of
If an operation is attempted, and an EEPROM device does not respond within 30 ms, the LAN89218
will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
Figure 3.11, "EEPROM Access Flow Diagram"
EEPROM Read or Write operation.
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
the EEPROM the host must first issue the EWEN command.
Busy Bit = 0
EEPROM Write
Figure 3.11 EEPROM Access Flow Diagram
Write Data
Command
Command
Register
Register
Register
Write
Read
Idle
DATASHEET
43
illustrates the host accesses required to perform an
EEPROM Read
Read Data
Command
Command
Register
Register
Register
Write
Read
Idle
Busy Bit = 0
Revision 1.3 (02-23-10)