LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 122

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
5.4.13
31:17
BITS
15:2
16
1
0
Reserved
TX Checksum Offload Engine Enable (TXCOE_EN). This bit enables/disables the Transmit COE.
This bit may only be changed if the TX data path is disabled.
0: The TXCOE is bypassed
1: The TXCOE is enabled
Reserved
RX Checksum Offload Engine Mode (RXCOE_MODE). This register indicates whether the RXCOE
will check for VLAN tags or a SNAP header prior to beginning its checksum calculation. In its default
mode, the calculation will always begin 14 bytes into the frame.
The RXCOE_MODE may only be changed if the RX data path is disabled.
0: Begin checksum calculation after first 14 bytes of Ethernet Frame
1: Begin checksum calculation at start of L3 packet by adjusting for VLAN tags and/or SNAP header.
RX Checksum Offload Engine Enable (RXCOE_EN). This bit enables/disables the Receive COE.
This bit may only be changed if the RX data path is disabled.
0: The RXCOE is bypassed
1: The RXCOE is enabled
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the
COE_CR—Checksum Offload Engine Control Register
This register controls the transmit and receive checksum offload engines.
Offset:
Default Value:
MAC_CR—MAC Control
simultaneously.
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
D
00000000h
Register) and vice versa. These functions cannot be enabled
DATASHEET
122
DESCRIPTION
Attribute:
Size:
R/W
32 bits
SMSC LAN89218
Datasheet