LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet
LAN89218AQ
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High-Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications PRODUCT FEATURES Highlights Designed and tested for automotive grade applications Integrated 10/100 MAC, PHY with HP Auto-MDIX support Interfaces to most 32-bit and 16-bit embedded CPU’s Integrated checksum offload engine Efficient architecture ...
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... LAN89218AQ (Tray) FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) LAN89218AQR (Tape & Reel) FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit TrueAuto™ ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table of Contents Chapter 1 General Description ...
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Hardware Reset Input (nRESET ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.2.1 RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet List of Figures Figure 1.1 System Block Diagram ...
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List of Tables Table 2.1 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table 7.8 LAN89218 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 1 General Description The LAN89218 is a full-featured, single-chip 10/100 Ethernet controller that has been designed to provide the highest performance possible for 32/16-bit applications. The LAN89218 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Embedded Microprocessor/ Microcontroller 1.1 Compatibility with LAN911x and LAN921x Device Families The LAN89218 is driver-, register-, and footprint-compatible with previous generation LAN911x and LAN921x device families. Drivers written for these ...
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Internal Block Overview This section provides an overview of the major functional blocks of the LAN89218, as shown in Figure 1.2, "Internal Block PME Wakup Indicator Power Management Host Bus Interface (HBI) SRAM I/F PIO Controller IRQ Interrupt Controller ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 1.4 10/100 Ethernet MAC The transmit and receive data paths are separate within the MAC allowing for the highest performance possible, especially in full duplex mode. The data paths connect ...
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GPIO Interface A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN89218 accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, ...
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... The package designators are: lll - Lot Sequence Code (optional Chip Revision Number yy - last two digits of Assembly Year ww - Assembly Work Week tttttttttttt - Tracking Number ( characters Country of Original Abbreviation (Optional - characters Free Symbol SMSC LAN89218 LAN89218AQ lllryyww tttttttttttt cc Figure 2.1 Pin Configuration (Top View) 15 DATASHEET 50 D10 ...
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Pin List NAME SYMBOL Host Data High D[31:16] Host Data Low D[15:0] Host Address A[7:1] Read Strobe nRD Write Strobe nWR Chip Select nCS Interrupt IRQ Request FIFO Select FIFO_SEL Endianess END_SEL Select Revision 1.3 (02-23-10) High Performance Single-Chip ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet NAME SYMBOL TPO+ TPO+ TPO- TPO- TPI+ TPI+ TPI- TPI- PHY External Bias EXRES1 Resistor Note: The pin names for the twisted pair pins shown above apply to a normal ...
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Table 2.3 Serial EEPROM Interface Signals NAME SYMBOL EEPROM Data, EEDIO/GPO3/ GPO3, TX_EN, TX_EN/TX_CLK (D32/nD16 TX_CLK, D32/nD16 EEPROM Chip EECS Select EEPROM Clock, EECLK/GPO4/ GPO4 RX_DV, RX_DV/RX_CLK RX_CLK Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet NAME SYMBOL Crystal 1, Clock In XTAL1/CLKIN Crystal 2 XTAL2 Reset nRESET Wakeup Indicator PME Auto-MDIX Enable AMDIX_EN 10/100 Selector SPEED_SEL No Connect NC Pull-Down PD (Reserved) SMSC LAN89218 Table ...
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Table 2.4 System and Power Signals (continued) NAME SYMBOL General Purpose GPIO[2:0]/ I/O data, nLED[3:1] nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), nLED3 (Full- Duplex Indicator ). RBIAS RBIAS Test Pin ATEST Internal Regulator VREG Power +3.3 V I/O ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table 2.4 System and Power Signals (continued) NAME SYMBOL PLL Power VDD_PLL PLL Ground VSS_PLL Reference Power VDD_REF Reference Ground VSS_REF Note 2.1 These pins must not be used to ...
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Table 2.6 100-TQFP Package Pin Assignments PIN PIN NUM PIN NAME NUM 1 GND_CORE 26 2 VREG 27 3 VDD_CORE 28 4 VSS_PLL 29 5 XTAL2 30 6 XTAL1 31 7 VDD_PLL 32 8 VDD_REF 33 9 ATEST 34 10 ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 2.2 Buffer Types TYPE Input pin I Schmitt triggered Input IS Output with 12 mA sink and 12 mA source O12 Open-drain output with 12 mA sink OD12 Open-drain output ...
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Chapter 3 Functional Description 3.1 10/100 Ethernet MAC The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host subsystem and the internal Ethernet PHY. The MAC ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet The receive and transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between the host interface and the MAC through which all transmitted and ...
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Virtual Local Area Network (VLAN) Support Virtual Local Area Networks or VLANs, as defined within the IEEE 802.3 standard, provide network administrators one means of grouping nodes within a larger network into broadcast domains. To implement a VLAN, four ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.3 Address Filtering Functional Description The Ethernet address fields of an Ethernet Packet, consists of two 6-byte fields: one for the destination address and one for the source address. The ...
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Filtering Modes 3.4.1 Perfect Filtering This filtering mode passes only incoming frames whose destination address field exactly matches the value programmed into the MAC Address High register and the MAC address low register. The MAC address is formed by ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.5 Wake-up Frame Detection Setting the Wake-up Frame Enable bit (WUEN) in the places the LAN89218 MAC in the wake-up frame detection mode. In this mode, normal data reception is ...
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Table 3.2 Wake-Up Frame Filter Register Structure Reserved Filter 3 Reserved Command Filter 3 Offset Filter 1 CRC-16 Filter 3 CRC-16 The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether or not ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet FIELD DESCRIPTION 7:0 Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame recognition. The minimum value of this field must ...
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Destination Address Source Address …………… ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Example frame configurations DST SRC 1DWORD DST SRC ...
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SSAP, CTRL, OUI[23:16 DST SRC 1DWORD Figure 3.6 Ethernet Frame with VLAN Tag and SNAP Header {DSAP, SSAP, CTRL, ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Note: Software applications must stop the receiver and flush the RX data path before changing the state of the RXCOE_EN or RXCOE_MODE bits. Note: When the RXCOE is enabled, automatic ...
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An example packet with a pre-pended TX checksum preamble can be found in 3.12.6.3, "TX Example four fragments, the first containing the TX Checksum Preamble. fragments are loaded into the TX Data FIFO. For more information on ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.7 Host Bus Operations 3.7.1 32-bit vs. 16-bit Host Bus Width Operation The LAN89218 can be configured to communicate with the host bus via either a 32-bit or a 16-bit ...
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Word Swap Function In addition to mixed endian functionality, the LAN89218 supports a Word Swap Function when its Host Bus Interface is configured to operate in 16-bit mode. This feature is controlled by the Word Swap register, which is ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 32-BIT BIG ENDIAN END_SEL = 1 INTERNAL ORDER MSB A[ HOST DATA BUS SMSC ...
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WORD_SWAP != FFFF_FFFFh (Disabled) 16-BIT BIG ENDIAN END_SEL = 1 INTERNAL ORDER MSB A[ A[ HOST DATA BUS WORD_SWAP = FFFF_FFFFh ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table 3.8 32-Bit Endian Ordering Logic Operation END_SEL = 0 END_SEL = 1 Table 3.9 16-Bit Endian Ordering Logic Operation 3.8 General Purpose Timer (GP Timer) The General Purpose Timer ...
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EEPROM Interface The LAN89218 can optionally load its MAC address from an external serial EEPROM properly configured EEPROM is detected by the LAN89218 at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will be ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM the host must first issue the EWEN command operation is attempted, ...
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Supported EEPROM Operations The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is provided below for each operation. ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) EWEN (Erase/Write Enable): ...
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READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA register. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) WRITE (Write Location): ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table 3.10, "Required EECLK each EEPROM operation. OPERATION ERASE ERAL EWDS EWEN READ WRITE WRAL 3.9.2.2 MAC Address Reload The MAC address can be reloaded from the EEPROM via a ...
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Power Management The LAN89218 supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.10.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.11, “Power ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.10.2.1 D1 Sleep Power consumption is reduced in this state by disabling clocks to portions of the internal logic as shown in Table 3.11. In this mode the clock to ...
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A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN89218 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.10.2.3 Power Management Event Indicators Figure 3. simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals. The pme_interrupt signal is used to ...
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Energy Detect Power-Down This power-down mode is activated by setting the Phy register bit 17. Please refer to 5.5.8, "Mode Control/Status," on page 128 no energy is present on the line, the PHY is powered down, with ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.11.1 Power-On Reset (POR) A Power-On reset occurs whenever power is initially applied to the LAN89218 power is removed and reapplied to the LAN89218. A timer within the ...
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PHY Reset Timing The following sections specify the operation and time required for the internal PHY to become operational after various resets or when returning from the reduced power state. 3.11.4.1 PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST) ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Upon completion of transmission, irrespective of success or failure, the status of the transmission is written to the TX status FIFO. TX status is available to the host and may ...
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TX Buffer Format TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.12.2 TX Command Format The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command precedes the data to be transmitted. The TX command is divided ...
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Table 3.13 TX Command 'A' Format (continued) BITS 10:0 Buffer Size (bytes). This field indicates the number of bytes contained in the buffer following this command. This value, along with the Buffer End Alignment field, is read and checked by ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.12.3 TX Data Format The TX data section begins at the third DWORD in the TX buffer (after TX command ‘A’ and TX command ‘B’). The location of the first ...
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TX Status Format TX status is passed to the host CPU through a separate FIFO mechanism. A status word is returned for each packet transmitted. Data transmission is suspended if the TX status FIFO becomes full. Data transmission will ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.12.5 Calculating Actual TX Data FIFO Usage The following rules are used to calculate the actual TX data FIFO space consumed Packet: TX command 'A' is stored ...
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Figure 3.22, "TX Example 1" how data is passed to the TX data FIFO. Ethernet Controller 31 TX Com m and 'A' Buffer End Alignment = 1 Data Start Offset = 7 First Segment = 1 Last Segment = 0 ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.12.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet single buffer as follows: 2-Byte “Data Start Offset” 183-Bytes of ...
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TX Example 3 In this example a single, 111-Byte Ethernet packet will be transmitted with a TX checksum. This packet is divided into four buffers. The four buffers are as follows: Buffer 0: 4-Byte “Data Start Offset” 4-Byte Checksum ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Data Written to the Ethernet Controller 31 TX Command 'A' Buffer End Alignment = 1 Data Start Offset = 4 First Segment = 1 Last Segment = 0 4-Byte Data ...
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Transmitter Errors If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation. TX Error (TXE) will be asserted under the following conditions: If the actual packet length count does not match the Packet ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet It is possible to read multiple packets out of the RX data FIFO in one continuous stream. It should be noted that the programmed Offset and Padding will be added ...
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Receive Data FIFO Fast Forward The RX data path implements an automatic data discard function. Using the RX data FIFO Fast Forward bit (RX_FFWD) in the RX_DP_CTRL register, the host can instruct the LAN89218 to skip the packet at ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.13.2 RX Packet Format The RX status words can be read from the RX status FIFO port, while the RX data packets can be read from the RX data FIFO. ...
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RX Status Format BITS 31 Reserved. This bit is reserved. Reads 0. 30 Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing filtering. 29:16 Packet Length. The size, in bytes, of the corresponding ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 3.13.4 Stopping and Starting the Receiver To stop the receiver, the host must clear the RXEN bit in the MAC Control Register. When the receiver is halted, the RXSTOP_INT will ...
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Chapter 4 Internal Ethernet PHY 4.1 Top Level Functional Description Functionally, the internal PHY can be divided into the following sections: 100Base-TX transmit and receive 10Base-T transmit and receive Internal MII interface to the Ethernet Media Access Controller Auto-negotiation to ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet CODE GROUP SYM 11110 0 0 01001 1 1 10100 2 2 10101 3 3 01010 4 4 01011 5 5 01110 6 6 01111 7 7 10010 8 8 ...
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CODE GROUP SYM 00011 V INVALID, RX_ER if during RX_DV 00101 V INVALID, RX_ER if during RX_DV 01000 V INVALID, RX_ER if during RX_DV 01100 V INVALID, RX_ER if during RX_DV 10000 V INVALID, RX_ER if during RX_DV 4.2.2 Scrambling ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 4.2.5 100M Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. ...
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NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 4.4.1 10M Transmit Data Across the Internal MII Bus The MAC controller drives the transmit data onto the internal TXD BUS. When the controller has driven TX_EN high to indicate ...
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Jabber Detection Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, that results in holding the TX_EN input for a long ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28. In summary, the PHY advertises 802.3 compliance ...
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Disabling Auto-Negotiation Auto-negotiation can be disabled by setting register 0, bit 12 to zero. The device will then force its speed of operation to reflect the information in register 0, bit 13 (speed) and register 0, bit 8 (duplex). ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Note 4.1 The LAN89218 10/100 PHY internal CRS signal operates in two modes: Active and Low. When in Active mode, the internal CRS will transition high and low upon line ...
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Chapter 5 Register Description The following section describes all LAN89218 registers and data ports. Base + 00h Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications FCh RESERVED B4h EEPROM Port B0h ACh A8h MAC CSR Port ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.1 Register Nomenclature and Access Attributes SYMBOL RO Read Only register is read only, writes to this register have no effect. WO Write Only register is ...
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TX FIFO Ports The TX Data Path consists of two FIFOs, TX Status and RX Data. The TX Status FIFO also has two ports at different locations. When the TX Status FIFO Port is read, the top of the ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table 5.1 Direct Address Register Map (continued) BASE ADDRESS + OFFSET SYMBOL A0h RX_DROP A4h MAC_CSR_CMD A8h MAC_CSR_DATA ACh AFC_CFG B0h E2P_CMD B4h E2P_DATA B8h - FCh RESERVED 5.3.1 ID_REV—Chip ...
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IRQ_CFG—Interrupt Configuration Register Offset: This register configures and indicates the state of the IRQ signal. BITS 31:24 Interrupt Deassertion Interval (INT_DEAS). This field determines the Interrupt Request Deassertion Interval in multiples of 10 µs. Setting this field to zero ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.3 INT_STS—Interrupt Status Register Offset: This register contains the current status of the generated interrupts. Writing the corresponding bits acknowledges and clears the interrupt. BITS 31 Software ...
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BITS Transmitter Error (TXE). 13 transmitter has encountered an error. Please refer to "Transmitter Errors," on page will cause a TXE. 12:11 Reserved 10 TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data FIFO is full, and another ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.4 INT_EN—Interrupt Enable Register Offset: This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits ...
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BYTE_TEST—Byte Order Test Register Offset: This register can be used to determine the byte ordering of the current configuration BITS 31:0 Byte Test 5.3.6 FIFO_INT—FIFO Level Interrupts Offset: This register configures the limits where the FIFO Controllers will generate ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.7 RX_CFG—Receive Configuration Register Offset: This register controls the LAN89218 receive engine. BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data ...
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TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN89218 Ethernet Controller. BITS 31:16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.9 HW_CFG—Hardware Configuration Register Offset: Note: The transmitter and receiver must be stopped before writing to this register. Refer to 3.12.8, "Stopping and Starting the Transmitter," on page 66 Starting ...
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BITS 0 Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset generates a full reset of the MAC CSR’s. The SCSR’s (system command and status registers) are reset except for any NASR bits. Soft reset also clears ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet TX DATA FIFO TX_FIF_SZ SIZE (BYTES) 2 1536 3 2560 4 3584 5 4608 6 5632 7 6656 8 7680 9 8704 10 9728 11 10752 12 11776 13 12800 ...
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RX_DP_CTRL—Receive Datapath Control Register Offset: This register is used to discard unwanted receive frames. BITS 31 RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes the RX data FIFO to fast-forward to the start of ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register Offset: This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN89218. BITS ...
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BITS 9 Wake-On-Lan Enable (WOL_EN) – When set, the PME signal (if enabled with PME_EN) will be asserted in accordance with the PME_IND bit upon a WOL event. When set, the PME_INT will also be asserted upon a WOL event, ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.14 GPIO_CFG—General Purpose IO Configuration Register Offset: This register configures the GPIO and LED functions. BITS 31 Reserved 30:28 LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an ...
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BITS 4:3 GPO Data 3-4 (GPODn). The value written is reflected on GPOn. GPO3 – bit 3 GPO4 – bit 4 2:0 GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is reflected on GPIOn. When read, ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.15 GPT_CFG-General Purpose Timer Configuration Register Offset: This register configures the General Purpose timer. The GP Timer can be configured to generate host interrupts at intervals defined in this register. ...
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WORD_SWAP—Word Swap Control Offset: This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs inside the LAN89218. The LAN89218 always sends data from the Transmit Data FIFO to the network so ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.19 RX_DROP– Receiver Dropped Frames Counter Offset: This register indicates the number of receive frames that have been dropped. BITS 31:0 RX Dropped Frame Counter (RX_DFC). This counter is incremented ...
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MAC_CSR_DATA – MAC CSR Synchronizer Data Register Offset: This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC CSR’s. BITS 31:0 MAC CSR Data. Value read from or written to ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.22 AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The ...
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BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN89218 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.3.23 E2P_CMD – EEPROM Command Register Offset: This register is used to control the read and write operations with the Serial EEPROM. BITS 31 EPC Busy: When ...
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BITS 30:28 EPC command. This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. A new command must not be issued until the previous command completes. This ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet BITS EPC Time-out EEPROM operation is performed, and there is no response from the EEPROM within 30 ms, the EEPROM controller will time- out and return to ...
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MAC Control and Status Registers These registers are located in the MAC module and are accessed indirectly through the MAC-CSR synchronizer port. Table 5.6, "MAC CSR Register accessible through the indexing method using the MAC_CSR_CMD and MAC_CSR_DATA registers (see ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.4.1 MAC_CR—MAC Control Register Offset: Default Value: This register establishes the RX and TX operation modes and controls for address filtering and packet filtering. BITS 31 Receive All Mode (RXALL). ...
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BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN89218 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet BITS 7:6 BackOff Limit (BOLMT). The BOLMT bits allow the user to set its back-off limit in a relaxed or aggressive mode. According to IEEE 802.3, the MAC has to ...
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ADDRH—MAC Address High Register Offset: Default Value: The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.4.3 ADDRL—MAC Address Low Register Offset: Default Value: The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The contents of this register ...
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HASHH—Multicast Hash Table High Register Offset: Default Value: The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.4.6 MII_ACC—MII Access Register Offset: Default Value: This register is used to control the Management cycles to the PHY. BITS 31:16 Reserved 15:11 PHY Address: For every access to this ...
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FLOW—Flow Control Register Offset: Default Value: This register controls the generation and reception of the Control (Pause command) frames by the MAC’s flow control block. The control frame fields are selected as specified in the 802.3x Specification and the ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.4.9 VLAN1—VLAN1 Tag Register Offset: Default Value: This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased from 1518 bytes ...
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WUFF—Wakeup Frame Filter Offset: Default Value: This register is used to configure the wake up frame filter. BITS 31:0 Wakeup Frame Filter (WFF). The Wakeup Frame Filter is configured through this register using an indexing mechanism. Following a reset, ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.4.12 WUCSR—Wake-up Control and Status Register Offset: Default Value: This register contains data pertaining to the MAC’s remote wake-up status and capabilities. BITS 31 WFF Pointer Reset (WFF_PTR_RST). This self-clearing ...
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COE_CR—Checksum Offload Engine Control Register Offset: Default Value: This register controls the transmit and receive checksum offload engines. BITS 31:17 Reserved 16 TX Checksum Offload Engine Enable (TXCOE_EN). This bit enables/disables the Transmit COE. This bit may only be ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC and MII_DATA registers. An index must be used to ...
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Basic Control Register Index (In Decimal): BITS 15 Reset software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. 14 Loopback loopback mode ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.5.2 Basic Status Register Index (In Decimal): BITS 15 100Base-T4 able ability 14 100Base-TX Full Duplex with full duplex, 0 ...
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PHY Identifier 2 Index (In Decimal): BITS 15:10 PHY ID Number b. Assigned to the 19th through 24th bits of the OUI. 9:4 Model Number. Six-bit manufacturer’s model number. 3:0 Revision Number. Four-bit manufacturer’s revision number. 5.5.5 Auto-negotiation Advertisement ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.5.6 Auto-negotiation Link Partner Ability Index (In Decimal): BITS 15 Next Page next page capable next page ability. This device does not support next page ...
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Auto-negotiation Expansion Index (In Decimal): BITS 15:5 Reserved 4 Parallel Detection Fault fault detected by parallel detection logic fault detected by parallel detection logic 3 Link Partner Next Page Able link partner ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.5.9 Special Modes Index (In Decimal): ADDRESS 15:8 Reserved 7:5 MODE: PHY Mode of operation. Refer to 4:0 PHYAD: PHY Address: The PHY Address is used for the SMI address. ...
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Special Control/Status Indications Index (In Decimal): ADDRESS 15 Override AMDIX Strap 0 - AMDIX_EN pin enables or disables HP Auto MDIX 1 - Override AMDIX_EN pin. PHY Register 27.14 and 27.13 determine MDIX function 14 Auto-MDIX Enable: Only effective ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 5.5.11 Interrupt Source Flag Index (In Decimal): BITS 15:8 Reserved. Ignore on read. 7 INT7. 1= ENERGYON generated, 0= not source of interrupt 6 INT6. 1= Auto-Negotiation complete, 0= not ...
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PHY Special Control/Status Index (In Decimal): BITS 15:13 Reserved 12 Autodone. Auto-negotiation done indication Auto-negotiation is not done or disabled (or not active Auto-negotiation is done 11:5 Reserved. Write as 0000010b, ignore on Read. 4:2 ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Chapter 6 Timing Diagrams 6.1 Host Interface Timing The LAN89218 supports the following host cycles: Read Cycles: PIO Reads (nCS or nRD controlled) PIO Burst Reads (nCS or nRD controlled) ...
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REGISTER NAME ID_REV IRQ_CFG INT_STS INT_EN BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT WORD_SWAP FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Table 6.1 ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 6.1.2 Special Restrictions on Back-to-Back Read Cycles There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In ...
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PIO Reads PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 6.3 PIO Burst Reads In this mode, performance is improved by allowing DWORD read cycles WORD read cycles back-to-back. PIO Burst Reads can be performed ...
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RX Data FIFO Direct PIO Reads In this mode, the upper address inputs are not decoded and any read of the LAN89218 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 6.5 RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN89218 will read the RX Data ...
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Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing SYMBOL DESCRIPTION t nCS, nRD Deassertion Time csh t nCS, nRD Valid to Data Valid csdv t Address Cycle Time acyc t Address, END_SEL, FIFO_SEL Setup to nCS, nRD ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 6.6 PIO Writes PIO writes are used for all LAN89218 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these ...
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TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN89218 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 6.8 nRESET Timing This diagram illustrates the nRESET pin timing requirements and its relation to the configuration strap pins. When used, it must be asserted for the minimum period specified. ...
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EEPROM Timing The following specifies the EEPROM timing requirements for the LAN89218: EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) EEDI (VERIFY) SYMBOL DESCRIPTION t EECLK Cycle time ckcyc t EECLK High time ckh t EECLK Low time ckl t EECS ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Chapter 7 Operational Characteristics Specifications are subject to change without notice. 7.1 Absolute Maximum Ratings* Supply Voltage (VDD_A, VDD_REF, VREG, VDD_IO ...
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Power Consumption (Device Only) This section provides typical power consumption values for the LAN89218 in various modes of operation. These measurements were taken under the following conditions: Temperature: .................................................................................................................................. +25 ° C Device VDD:....................................................................................................................................+3.3 V Table 7.2 Power Consumption ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 7.5 Power Consumption (Device and System Components) This section provides typical power consumption values for a complete Ethernet interface based on the LAN89218, including the power dissipated by the magnetics ...
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DC Electrical Specifications Table 7.4 below lists the worst case current consumption for each of the supplies of the LAN89218. These figures are provided to assist system designers properly design the power supply; they cannot be used to determine ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table 7.5 I/O Buffer Characteristics (continued) PARAMETER SYMBOL IS Type Input Buffer Negative-Going Threshold V ILT Positive-Going Threshold V IHT Schmitt Trigger Hysteresis V HYS ( IHT - ...
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Table 7.6 100BASE-TX Transceiver Characteristics PARAMETER Peak Differential Output Voltage High Peak Differential Output Voltage Low Signal Amplitude Symmetry Signal Rise & Fall Time Rise & Fall Time Symmetry Duty Cycle Distortion Overshoot & Undershoot Jitter Note 7.7 Measured at ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 7.7 Clock Circuit The LAN89218 can accept either a 25 MHz crystal (preferred MHz single-ended clock oscillator ( ± 50 PPM) input. The LAN89218 shares the 25 ...
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Chapter 8 Package Outline 8.1 100-TQFP Package Figure 8.1 100-Pin TQFP Package Definition Table 8.1 100-Pin TQFP Package Parameters MIN NOMINAL 0. 1. 15. 13. 15. ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Chapter 9 Revision History REVISION LEVEL AND DATE SECTION/FIGURE/ENTRY Rev. 1.3 Power-On Timing Diagram (02-23-10) Section 3.11.1, "Power-On Reset (POR)," on page 53 Section 6.8, "nRESET Timing," on page 143 ...
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Table 9.1 Customer Revision History (continued) REVISION LEVEL AND DATE SECTION/FIGURE/ENTRY Rev. 1.2 All (11-21-08) Table 7.8 on page 151 Rev. 1.2 Section 5.3.23, "E2P_CMD – (11-21-08) EEPROM Command Register," on page 107 Chapter 7, "Operational Characteristics," on page 145 ...
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High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Chapter 10 Further Information For more information on SMSC automotive products, including integrated circuits, software, and MOST development tools and modules, visit our web site: http://www.smsc-ais.com. Direct contact information is ...