LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 16

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
2.1
Host Data High
Host Data Low
Host Address
Read Strobe
Write Strobe
FIFO Select
Chip Select
Endianess
Interrupt
Request
NAME
Select
Pin List
FIFO_SEL
END_SEL
SYMBOL
D[31:16]
D[15:0]
A[7:1]
nWR
nRD
nCS
IRQ
BUFFER
O8/OD8
Table 2.1 Host Bus Interface Signals
TYPE
(PD)
(PD)
I/O8
I/O8
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
IS
IS
IS
IS
IS
IS
DATASHEET
PINS
16
16
#
7
1
1
1
1
1
1
16
Bi-directional data port.
Note that Pull-down’s are disabled in 32-bit mode.
Bi-directional data port.
7-bit Address Port. Used to select Internal CSR’s and
TX and RX FIFOs.
Active low strobe to indicate a read cycle.
Active low strobe to indicate a write cycle. This signal,
qualified with nCS, is also used to wakeup the
LAN89218 when it is in a reduced power state.
Active low signal used to qualify read and write
operations. This signal qualified with nWR is also used
to wakeup the LAN89218 when it is in a reduced power
state.
Programmable Interrupt request. Programmable
polarity, source and buffer types.
When driven high all accesses to the LAN89218 are to
the RX or TX Data FIFOs. In this mode, the A[7:3]
upper address inputs are ignored.
Endianess Select: When low, all host bus accesses
follow little endian byte ordering. When high, all
accesses follow big endian byte ordering.
This signal is qualified with nCS and nRD for read
operations, and is qualified with nCS and nWR for write
operations. This signal has the same timing
characteristics as the address inputs.
Note: This signal is pulled low internally and may be
left unconnected or connected to ground for
compatibility with earlier devices.
DESCRIPTION
SMSC LAN89218
Datasheet