LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 106

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
BITS
0
Flow Control on Any Frame (FCANY). When this bit is set, the LAN89218
will assert back pressure, or transmit a pause frame when the AFC level is
reached and any frame is received. Setting this bit enables full-duplex flow
control when the LAN89218 is operating in full-duplex mode.
When this mode is enabled during half-duplex operation, the Flow Controller
does not decode the MAC address and will send a pause frame upon
receipt of a valid preamble (i.e., immediately at the beginning of the next
frame after the RX data FIFO level is reached).
When this mode is enabled during full-duplex operation, the Flow Controller
will immediately instruct the MAC to send a pause frame when the RX data
FIFO level is reached. The MAC will queue the pause frame transmission
for the next available window.
Setting this bit overrides bits [3:1] of this register.
[19:16]
Ah
Bh
Ch
Dh
Eh
Fh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Table 5.5 Backpressure Duration Bit Mapping
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
DESCRIPTION
100 Mbps Mode
DATASHEET
100 µs
150 µs
200 µs
250 µs
300 µs
350 µs
400 µs
450 µs
500 µs
550 µs
600 µs
10 µs
15 µs
25 µs
50 µs
5 µs
106
BACKPRESSURE DURATION
10 Mbps Mode
102.2 µs
152.2 µs
202.2 µs
252.2 µs
302.2 µs
352.2 µs
402.2 µs
452.2 µs
502.2 µs
552.2 µs
602.2 µs
12.2 µs
17.2 µs
27.2 µs
52.2 µs
TYPE
7.2 µs
R/W
SMSC LAN89218
DEFAULT
Datasheet
0