LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 136

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
6.2
SYMBOL
A[7:1], END_SEL
t
t
t
t
t
cycle
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
nCS, nRD
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles
is identical with the exception that D[31:16] are not driven during a 16-bit read.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, END_SEL Setup to nCS, nRD Valid
Address, END_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
t
Figure 6.1 PIO Read Cycle Timing
asu
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Table 6.3 PIO Read Timing
DATASHEET
t
don
t
csdv
136
t
csl
t
cycle
MIN
t
45
32
13
doh
0
0
0
0
t
ah
TYP
t
t
doff
csh
MAX
30
7
SMSC LAN89218
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns