LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 55

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
Upon completion of transmission, irrespective of success or failure, the status of the transmission is
written to the TX status FIFO. TX status is available to the host and may be read using PIO operations.
An interrupt can be optionally enabled by the host to indicate the availability of a programmable
number TX status DWORDS.
Before writing the TX command and payload data to the TX FIFO, the host must check the available
TX FIFO space by performing a PIO read of the TX_FIFO_INF register. The host must ensure that it
does not overfill the TX FIFO or the TX Error (TXE) flag will be asserted.
The host proceeds to write the TX command by first writing TX command ‘A’, then TX command ‘B’.
After writing the command, the host can then move the payload data into the TX FIFO. TX status
DWORD’s are stored in the TX status FIFO to be read by the host at a later time upon completion of
the data transmission onto the wire.
Last Buffer in
Figure 3.20 Simplified Host TX Flow Diagram
Packet
DATASHEET
Command
(optional)
available
Padding
Check
space
Buffer
Write
FIFO
Write
Write
Start
Idle
init
TX
55
TX Status
Available
Not Last Buffer
(optional)
Read TX
Status
Revision 1.3 (02-23-10)