LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 12

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
1.2
1.3
Wakup Indicator
SRAM I/F
FIFO_SEL
PME
IRQ
This section provides an overview of the major functional blocks of the LAN89218, as shown in
Figure 1.2, "Internal Block
The LAN89218 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in
either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
Internal Block Overview
10/100 Ethernet PHY
Host Bus Interface
Power Management
PIO Controller
GP Timer
Controller
Interrupt
(HBI)
Figure 1.2 Internal Block Diagram
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Diagram".
Configurable RX FIFO
Configurable TX FIFO
RX Status FIFO
TX Status FIFO
2 kB to 14 kB
2 kB to 14 kB
Core Regulator
3.3 V to 1.8 V
DATASHEET
+3.3 V
12
25 MHz
PLL
Ethernet
Buffer - 128 bytes
Buffer – 2 kbytes
10/100
MIL - TX Elastic
Offload Engine
MIL - RX Elastic
Offload Engine
TX Checksum
RX Checksum
MAC
PLL Regulator
3.3 V to 1.8 V
+3.3 V
Ethernet
10/100
PHY
EEPROM
(Optional)
EEPROM
Controller
SMSC LAN89218
Datasheet
LAN