LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 20

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
Internal Regulator
Activity Indicator),
+3.3 V I/O Power
General Purpose
Analog Ground
nLED1 (Speed
nLED2 (Link &
+3.3 V Analog
nLED3 (Full-
Core Voltage
Core Ground
I/O Ground
Decoupling
Indicator
Indicator),
Test Pin
I/O data,
Duplex
RBIAS
NAME
Power
Power
).
GND_CORE
VDD_CORE
GPIO[2:0]/
nLED[3:1]
SYMBOL
GND_IO
VDD_IO
ATEST
RBIAS
VDD_A
VSS_A
VREG
Table 2.4 System and Power Signals (continued)
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
BUFFER
IS/O12/
TYPE
OD12
AI
P
P
P
P
P
P
P
I
DATASHEET
20
PINS
NUM
1
1
3
1
8
8
3
4
2
2
+3.3 V analog power supply pins.
Ground for internal digital logic
General Purpose I/O data: These three
general-purpose signals are fully programmable
as either push-pull output, open-drain output or
input by writing the GPIO_CFG configuration
register in the CSR’s. They are also multiplexed
as GP LED connections.
GPIO signals are Schmitt-triggered inputs.
When configured as LED outputs these signals
are open-drain and the input buffers are
disabled.
nLED1 (Speed Indicator). This signal is driven
low when the operating speed is 100 Mbps,
during auto-negotiation and when the cable is
disconnected. This signal is driven high only
during 10 Mbps operation.
nLED2 (Link & Activity Indicator). This signal
is driven low (LED on) when the LAN89218
detects a valid link. This signal is pulsed high
(LED off) for 80 ms whenever transmit or
receive activity is detected. This signal is then
driven low again for a minimum of 80 ms, after
which time it will repeat the process if TX or RX
activity is detected. Effectively, LED2 is
activated solid for a link. When transmit or
receive activity is sensed LED2 will flash as an
activity indicator.
nLED3 (Full-Duplex Indicator). This signal is
driven low when the link is operating in full-
duplex mode.
PLL Bias: Connect to an external 12.0 kΩ 1.0%
resistor to ground. Used for the PLL Bias circuit.
This pin must be connected to VDD for normal
operation.
3.3 V input for internal voltage regulator
+3.3 V I/O logic power supply pins
Ground for I/O pins
Ground for analog circuitry
+1.8 V from internal core regulator. Both pins
must be connected together externally. Each
pin requires a 0.01 µF decoupling capacitor. In
addition, pin 3 requires a bulk 10uF capacitor
(<2 Ω ESR) in parallel.
DESCRIPTION
(Note
2.1)
SMSC LAN89218
Datasheet