LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 142

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
6.7
A[2:1], END_SEL
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
FIFO_SEL
nCS, nWR
Data Bus
In this mode the upper address inputs are not decoded, and any write to the LAN89218 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN89218. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-
bit write. Note that address lines A[2:1] are still used when the LAN89218 is operating in 32-bit and
16-bit mode. Address bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
TX Data FIFO Direct PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, END_SEL, FIFO_SEL Setup to nCS, nWR
Assertion
Address, END_SEL, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Table 6.8 TX Data FIFO Direct PIO Write Timing
t
asu
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142
t
csl
t
t
cycle
dsu
MIN
45
32
13
0
0
7
0
t
dh
t
ah
TYP
t
csh
MAX
SMSC LAN89218
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns