LAN89218AQ Standard Microsystems (SMSC), LAN89218AQ Datasheet - Page 140

• Manufacturer Part Number: LAN89218AQ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN89218AQ

• Lead Free Status / RoHS Status: Compliant

Revision 1.3 (02-23-10)
SYMBOL
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, END_SEL, FIFO_SEL Setup to nCS, nRD
Valid
Address Stable to Data Valid
Address, END_SEL, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
DATASHEET
140
MIN
13
45
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN89218
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns