LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 85

• Manufacturer Part Number: LAN9420I-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420I-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
4.1
REGISTER BIT TYPE
RESERVED
NOTATION
NASR
Register Nomenclature
WO
WC
RO
RC
SC
LH
LL
W
R
Table 4.1
Register attribute examples:
R/W: Can be written. Will return current setting on a read.
R/WC: Will return current setting on a read. Writing a one clears the bit.
describes the register bit attributes used throughout this section.
Read: A register or bit with this attribute can be read.
Write: A register or bit with this attribute can be written.
Read only: Read only. Writes have no effect.
Write only: If a register or bit is write-only, reads will return unspecified data.
Write One to Clear: writing a one clears the value. Writing a zero has no effect
Read to Clear: Contents is cleared after the read. Writes have no effect.
Latch Low: This mode is used by the Ethernet PHY registers. Bits with this attribute
will stay low until the bit is read. After a read, the bit will remain low, but will change
to high if the condition that caused the bit to go low is removed. If the bit has not been
read the bit will remain low regardless of if its cause has been removed.
Latch High: This mode is used by the Ethernet PHY registers. Bits with this attribute
will stay high until the bit is read. After a read, the bit will remain high, but will change
to low if the condition that caused the bit to go high is removed. If the bit has not been
read the bit will remain high regardless of if its cause has been removed.
Self-Clearing: Contents is self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
Not Affected by Software Reset. The state of NASR bits does not change on asser-
tion of a software reset.
Reserved Field: Certain bits within registers are listed as “RESERVED”. Unless
stated otherwise, these bits must be written with zero for future compatibility. The val-
ues of these bits are not guaranteed when read.
Reserved Address: Certain addresses with the device are listed as “RESERVED”.
Unless otherwise noted, do not read from or write to reserved addresses.
Table 4.1 Register Bit Types
DATASHEET
REGISTER BIT DESCRIPTION
85
Revision 1.4 (12-17-08)