LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 63

• Manufacturer Part Number: LAN9420I-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420I-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.5.5.1
3.5.6
31:28
27:16
15:12
BITS
RX Checksum Calculation
The checksum is calculated 16 bits at a time. In the case of an odd sized frame, an extra byte of zero
is used to pad up to 16 bits.
Consider the following packet: DA, SA, Type, B0, B1, B2 … BN, FCS
Let [A, B] = A*256 + B;
If the packet has an even number of octets then
checksum = [B1, B0] + C0 + [B3, B2] + C1 + … + [BN, BN-1] + CN-1
Where C0, C1, ... CN-1 are the carry out results of the intermediate sums.
If the packet has an odd number of octets then
checksum = [B1, B0] + C0 + [B3, B2] + C1 + … + [0, BN] + CN-1
Transmit Checksum Offload Engine (TXCOE)
The transmit checksum offload engine (TXCOE) provides assistance to the Host by calculating a 16-
bit checksum, typically for TCP, for a transmit Ethernet frame. The TXCOE calculates the checksum
and inserts the results back into the data stream as it is transferred to the MAC.
When bit 27 of TDES1 (CK bit) is set in conjunction with bit 29 of TDES1 (FS bit) and bit 16 of the
COE_CR register (TX_COE_EN), the TXCOE will perform a checksum calculation on the associated
packet. When these three bits are set, a 32-bit TX checksum preamble must be pre-pended to the
beginning of the TX packet (refer to
the handling of the associated packet. Bits 11:0 of the TX checksum preamble define the byte offset
at which the data checksum calculation will begin. The checksum calculation will begin at this offset
and will continue until the end of the packet. The data checksum calculation must not begin in the MAC
header (first 14 bytes) or in the last 4 bytes of the TX packet. When the calculation is complete, the
checksum will be inserted into the packet at the byte offset defined by bits 27:16 of the TX checksum
preamble. The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4
bytes of the TX packet.
If the TX packet already includes a partial checksum calculation (perhaps inserted by an upper layer
protocol), this checksum can be included in the hardware checksum calculation by setting the TXCSSP
field in the TX checksum preamble to include the partial checksum. The partial checksum can be
replaced by the completed checksum calculation by setting the TXCSLOC pointer to point to the
location of the partial checksum.
Note: The TXCOE_MODE may only be changed if the TX path is disabled. If it is desired to change
Note: The TX checksum preamble must be DWORD-aligned.
RESERVED
TXCSLOC - TX Checksum Location
This field specifies the byte offset where the TX checksum will be inserted in the TX packet. The
checksum will replace two bytes of data starting at this offset.
Note:
RESERVED
this value during run time, it is safe to do so only after the DMA is disabled and the MIL is
empty.
The TX checksum cannot be inserted in the MAC header (first 14 bytes) or in the last 4
bytes of the TX packet.
Table 3.20 TX Checksum Preamble
DATASHEET
Table
3.20). The TX checksum preamble instructs the TXCOE on
63
DESCRIPTION
Revision 1.4 (12-17-08)