LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet
LAN9420I-NU
Specifications of LAN9420I-NU
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LAN9420I-NU Summary of contents
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... Automatic payload padding and pad removal — Loop-back modes — Flexible address filtering modes – One 48-bit perfect address – 64 hash-filtered multicast addresses – Pass all multicast SMSC LAN9420/LAN9420i LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface – Promiscuous mode – ...
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... LAN9420-NU FOR 128-PIN VTQFP, LEAD-FREE ROHS COMPLIANT PACKAGE ( LAN9420i-NU FOR 128-PIN VTQFP, LEAD-FREE ROHS COMPLIANT PACKAGE (-40 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... Supported EEPROM Operations .............................................................................. 33 3.3.5.3.2 Host Initiated MAC Address, SSID, SSVID Reload .................................................. 37 3.3.5.3.3 EEPROM Command and Data Registers .................................................................37 3.3.5.3.4 EEPROM Timing....................................................................................................... 37 3.3.6 System Control and Status Registers (SCSR 3.4 DMA Controller (DMAC 3.4.1 DMA Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SMSC LAN9420/LAN9420i 3 DATASHEET Revision 1.4 (12-17-08) ...
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... Transmit Data Across the Internal MII Bus ............................................................ 69 3.6.3.2 Manchester Encoding .................................................................................................... 69 3.6.3.3 10M Transmit Drivers..................................................................................................... 69 3.6.4 10BASE-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.6.4.1 10M Receive Input and Squelch .................................................................................... 69 3.6.4.2 Manchester Decoding .................................................................................................... 69 3.6.4.3 Jabber Detection ............................................................................................................ 70 3.6.5 Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 4 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
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... Free Run Counter (FREE_RUN 4.2.11 EEPROM Command Register (E2P_CMD 4.2.12 EEPROM Data Register (E2P_DATA 102 4.3 DMAC Control and Status Registers (DCSR 103 4.3.1 Bus Mode Register (BUS_MODE 104 SMSC LAN9420/LAN9420i G3 ................................................................................................. 75 D0A............................................................................................... 76 D3HOT.......................................................................................... 77 D3COLD ....................................................................................... 78 5 DATASHEET Revision 1.4 (12-17-08) ...
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... D3 - PHY in General Power Down Mode 158 5.3.5 Maximum Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 5.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.5.1 Equivalent Test Load (Non-PCI Signals 161 5.6 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 6 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
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... Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.7 PCI I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.8 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.9 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Chapter 6 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.1 128-VTQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Chapter 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 SMSC LAN9420/LAN9420i 7 DATASHEET Revision 1.4 (12-17-08) ...
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... List of Figures Figure 1.1 System Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 1.2 LAN9420/LAN9420i Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2.1 LAN9420/LAN9420i 128-VTQFP (Top View Figure 3.1 PCI Bridge Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 3.2 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3.3 CSR Double Endian Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 3.4 I/O Bar Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 3 ...
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... Table 5.7 100BASE-TX Transceiver Characteristics 160 Table 5.8 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 5.9 PCI Clock Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 5.10 PCI I/O Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 5.11 PCI I/O Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 5.12 EEPROM Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SMSC LAN9420/LAN9420i 9 DATASHEET Revision 1.4 (12-17-08) ...
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... Table 5.13 LAN9420/LAN9420i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 6.1 LAN9420/LAN9420i 128-VTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 10 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
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... Status Registers Interrupt Power System Control & Controller Management Status Registers (INT) (PM) LAN9420/LAN9420i Figure 1.2 LAN9420/LAN9420i Internal Block Diagram SMSC LAN9420/LAN9420i LAN9420/LAN9420i External PCI Device 25MHz Crystal PCI Device Figure 1.1 System Level Block Diagram Ethernet MAC TX DMA Engine TX FIFO (2KB) ...
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... These include a multipurpose 16-bit configurable General Purpose Timer (GPT), a Free-Run Counter, a 3-pin configurable GPIO/LED interface, and 2 GPO pins. All aspects of LAN9420/LAN9420i are managed via a set of memory mapped control and status registers. LAN9420/LAN9420i’s performance and features make it an ideal solution for many applications in the consumer electronics, enterprise, and industrial automation markets ...
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... PCI Bridge LAN9420/LAN9420i implements a PCI Local Bus Specification Revision 3.0 compliant interface, supporting the PCI Bus Power Management Interface Specification Revision 1.1. It provides the PCI Configuration Space Control and Status registers used to configure LAN9420/LAN9420i for PCI device operation. Please refer to 1.4 ...
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... Please refer to on page 30 for more information. 1.7.6 Free Run Counter The Free Run Counter has no dedicated function within LAN9420/LAN9420i and may be used by the software drivers as a timebase. Please refer to for more information. 1.8 Control and Status Registers (CSR) LAN9420/LAN9420i’ ...
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... PWRGOOD 121 VAUXDET 122 GPIO0/nLED1 123 NC 124 NC 125 NC 126 NC 127 NC 128 NOTE: When HP Auto-MDIX is activated, the TPO+/- pins function as TPI+/- and vice-versa. Figure 2.1 LAN9420/LAN9420i 128-VTQFP (Top View) SMSC LAN9420/LAN9420i SMSC LAN9420/LAN9420i 128-VTQFP TOP VIEW 15 DATASHEET AD15 62 nCBE1 61 PAR 60 nSERR ...
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... This pin is pulled low through an internal pull- down resistor IS PCI Auxiliary Voltage Sense: This pin is used to sense (PD) the presence of a 3.3V auxiliary supply in order to define the PME support available. Note: This pin is pulled low through an internal pull- down resistor 16 DATASHEET Datasheet DESCRIPTION SMSC LAN9420/LAN9420i ...
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... PCInRST following power up. The “IS” input buffer type is enabled only during power up. The “IS” input buffer type is disabled at all other times. SMSC LAN9420/LAN9420i Table 2.2 EEPROM BUFFER TYPE ...
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... OD12 nLED2 (Link & Activity Indicator): This pin can also function as the Ethernet Link and Activity Indicator LED and is driven low (LED on) when LAN9420/LAN9420i detects a valid link. This pin is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This pin is then driven low again for a minimum of 80mS, after which time it will repeat the process activity is detected ...
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... Data In Positive External EXRES 1 PHY Bias Resistor SMSC LAN9420/LAN9420i Table 2.5 PLL and Ethernet PHY Pins BUFFER TYPE ICLK Crystal Input: External 25MHz crystal input. This pin can also be driven by a single-ended clock oscillator. When this method is used, XO should be left unconnected. ...
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... Master Bias Power Supply Refer to the LAN9420/LAN9420i application note for additional connection information. P +3.3V Power Supply for I/O Pins and Internal Regulator Refer to the LAN9420/LAN9420i application note for additional connection information. P Common Ground for I/O Pins, Core, and Analog Circuitry P Digital Core +1 ...
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... AD30 55 24 AD29 56 25 AD28 57 26 AD27 58 27 VSS 59 28 VDD33IO 60 29 AD26 61 30 AD25 62 31 AD24 SMSC LAN9420/LAN9420i PIN PIN NAME NUM PIN NAME nCBE3 65 AD14 IDSEL 66 VSS VSS 67 VDD33IO VDD33IO 68 AD13 AD23 69 AD12 AD22 70 AD11 AD21 71 AD10 AD20 72 AD9 ...
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... Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to LAN9420/LAN9420i. When connected to a load that must be pulled high, an external resistor must be added. PD 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull- downs are always enabled ...
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... Figure 1.2 LAN9420/LAN9420i Internal Block Diagram on page 3.2 PCI Bridge (PCIB) The PCI Bridge (PCIB) facilitates LAN9420/LAN9420i’s operation on a PCI bus as a device. It has the following features: PCI Master Interface: This interface connects LAN9420/LAN9420i to the PCI bus when it is functioning as a PCI Master used by the DMA engines to directly access the PCI Host’s memory. ...
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... Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PCI Bridge (PCIB) PCI Configuration Space CSR Figure 3.1 PCI Bridge Block Diagram 24 DATASHEET Datasheet To/From DMAC Arbiter To/From CSR Blocks PM Related Signals (To/From PM) PM Signal (From PM) SMSC LAN9420/LAN9420i ...
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... PCI Interface Environments The PCIB supports only Device operation. It functions as a simple bridge, permitting LAN9420/LAN9420i to act as a master/target PCI device on the PCI bus. The Host performs PCI arbitration and is responsible for initializing configuration space for all devices on the bus. illustrates Device operation. ...
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... The Host initializes and configures the PCI Device during a plug-and-play process. The PCI Target Interface supports 32-bit slave accesses only. Non 32-bit PCI target reads to LAN9420/LAN9420i will result in a full 32-bit read. Non 32-bit PCI target writes to LAN9420/LAN9420i will be silently discarded. ...
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... PCI Discard Timer When the PCI master performs a read of LAN9420/LAN9420i, the PCI Bridge will fetch the data and acknowledge the PCI transfer when data is available. If the PCI master malfunctions and does complete the transaction within 32768 PCI clocks, LAN9420/LAN9420i will flush the data to prevent a potential bus lock-up ...
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... EEPROM Controller (EPC): An optional, external, Serial EEPROM may be used to store the default values for the MAC address, PCI Subsystem ID, and PCI Subsystem Vendor ID. In addition, it may also be used for general data storage. The EEPROM controller provides LAN9420/LAN9420i access to the EEPROM and permits the Host to read, write and erase its contents. ...
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... Registers (SCSR) block. The interrupt status register (INT_STS) reflects the current state of the interrupt sources prior to qualification with their associated enables. The SW_INT, MBERR_INT, SBERR_INT, GPIOx_INT, and GPT_INT are latched, and are cleared through the SCSR block upon a SMSC LAN9420/LAN9420i Figure 3.6 Interrupt Controller ...
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... If enabled, the wake detection logic is able to generate an interrupt to the PCI Bridge on detection of a MAC wakeup event (Wakeup Frame or Magic Packet Ethernet link status change (energy detect). Note: LAN9420/LAN9420i can optionally generate a PCI interrupt in addition to assertion of nPME on detection of a power management event. Generation of a PCI interrupt is not the typical usage. ...
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... When the FRC reaches a value of FFFF_FFFFh, it wraps around to 0000_0000h and continues counting. The FRC is operational in all power states. The FRC has no fixed function in LAN9420/LAN9420i and is ideal for use by drivers as a timebase. The current FRC count is readable in FREE_RUN SCSR. Please refer to for more information on this register. ...
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... The signature value of 0xA5 is stored at address 0. A different signature value indicates to the EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to LAN9420/LAN9420i. In this case, following default values are used for the Subsystem Device ID (SSID), Subsystem Vendor ID (SSVID), and the MAC address. VARIABLE ...
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... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the Host must first issue the EWEN command operation is attempted, and an EEPROM device does not respond within 30mS, LAN9420/LAN9420i will timeout, and the EPC Time-out bit (EPC_TO) in the E2P_CMD register will be set. Figure 3.7 illustrates the Host accesses required to perform an EEPROM Read or Write operation ...
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... EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Figure 3.8 EEPROM ERASE Cycle Figure 3.9 EEPROM ERAL Cycle 34 DATASHEET Datasheet t CSL t CSL SMSC LAN9420/LAN9420i ...
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... Disable” command is sent, or until power is cycled. Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) SMSC LAN9420/LAN9420i Figure 3.10 EEPROM EWDS Cycle 1 ...
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... EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Figure 3.12 EEPROM READ Cycle Figure 3.13 EEPROM WRITE Cycle 36 DATASHEET Datasheet t CSL CSL D0 SMSC LAN9420/LAN9420i ...
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... Data Register (E2P_DATA)," on page 102 Supported EEPROM operations are described in these sections. 3.3.5.3.4 EEPROM TIMING Refer to Section 5.8, "EEPROM Timing," on page 165 SMSC LAN9420/LAN9420i Figure 3.14 EEPROM WRAL Cycle Cycles", shown below, shows the number of EECLK cycles required for Table 3 ...
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... The DMAC and the driver communicate through two data structures: DMA Control and Status Registers (DCSR), as described in Registers (DCSR)," on page Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Section 4.3, "DMAC Control and Status 103. 38 DATASHEET Datasheet for a complete SMSC LAN9420/LAN9420i ...
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... The DMAC will skip to the next frame buffer when end of frame is detected. Data chaining can be enabled or disabled. The ring and chain type descriptor structures are illustrated in Note: Descriptors of zero buffer length are not supported at the initial and final descriptors of a chain. SMSC LAN9420/LAN9420i 39 DATASHEET Figure 3 ...
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... Ring Structure: Chain Structure: Figure 3.15 Ring and Chain Descriptor Structures Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface BUFFER 1 DESCRIPTOR 0 BUFFER 2 BUFFER 1 DESCRIPTOR 1 BUFFER 2 BUFFER 1 DESCRIPTOR n BUFFER 2 BUFFER 1 DESCRIPTOR 0 BUFFER 1 DESCRIPTOR 1 NEXT DESCRIPTOR 40 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
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... MAC control register (MAC_CR). This bit is only valid when the last descriptor (LS) bit is set and the received frame is greater than or equal to 64 bytes in length. Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. SMSC LAN9420/LAN9420i ...
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... When set, indicates that the buffers pointed to by this descriptor are the last buffers of the frame. Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.5 RDES0 Bit Fields (continued) DESCRIPTION 42 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
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... Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. 0 RESERVED Host Actions: Cleared on writes and ignored on reads. DMAC Actions: Ignored on reads and cleared on writes. SMSC LAN9420/LAN9420i Table 3.5 RDES0 Bit Fields (continued) DESCRIPTION 43 DATASHEET Revision 1.4 (12-17-08) ...
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... DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer address. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.6 RDES1 Bit Fields DESCRIPTION (RX_BASE_ADDR). Table 3.7 RDES2 Bit Fields DESCRIPTION 44 DATASHEET Datasheet Receive List SMSC LAN9420/LAN9420i ...
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... Figure 3.17 shows the Transmit Descriptor format. OW RESERVED TDES0 TDES1 TDES2 TDES3 SMSC LAN9420/LAN9420i Table 3.8 RDES3 Bit Fields DESCRIPTION ES RES TBS2 BUFFER 1 ADDRESS POINTER BUFFER 2 ADDRESS POINTER Figure 3.17 Transmit Descriptor 45 DATASHEET TBS1 Revision 1.4 (12-17-08) ...
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... When set, indicates that the frame transmission was aborted due to collision occurring after the collision window of 64 bytes. Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.9 TDES0 Bit Fields DESCRIPTION 46 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
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... When set, indicates that the buffer contains the first segment of a frame. Host Actions: Initializes this bit. DMAC Actions: Reads this bit to determine whether the buffer contains the first segment of a frame. SMSC LAN9420/LAN9420i Table 3.9 TDES0 Bit Fields (continued) DESCRIPTION Table 3.10 TDES1 Bit Fields ...
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... DMAC Actions: Reads this field to determine the allocated size of associated data buffer. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 3.10 TDES1 Bit Fields (continued) DESCRIPTION 63. 48 DATASHEET Datasheet Section 3.5.6, "Transmit Transmit List Base SMSC LAN9420/LAN9420i ...
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... The receive and transmit engines begin processing receive and transmit operations. 5. Set bit 2 (RXEN) of MAC_CR to turn the receiver on. 6. Set bit 3 (TXEN) of MAC_CR to turn the transmitter on. SMSC LAN9420/LAN9420i Table 3.11 TDES2 Bit Fields DESCRIPTION Table 3.12 TDES3 Bit Fields ...
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... Descriptor acquisition is attempted if any of the following conditions are satisfied: When the (SR) Start/Stop Receive bit (bit 1 of DMAC_CONTROL) sets immediately after being placed in the running state Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 50 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
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... MAC_CR to turn the receiver off, then clear bit 1 (SR) of DMAC_CONTROL to stop RX DMA). Performing these steps in the reverse order will result in RX DMA not stopping (DMAC_STATUS will continue to show the Receive Process State (RS) as Running and Receive Process Stopped (RPS) does not assert). SMSC LAN9420/LAN9420i 51 DATASHEET Revision 1.4 (12-17-08) ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to LAN9420/LAN9420i. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... These features include the ability to disable retries after a collision, dynamic FCS (Frame Check Sequence) generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic SMSC LAN9420/LAN9420i 53 DATASHEET Revision 1.4 (12-17-08) ...
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... Interface of the PCIB. On the backend, the MAC interfaces with the 10/100 PHY through an MII (Media Independent Interface) port which is internal to LAN9420/LAN9420i. The MCSR also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. ...
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... If the frame fails the filter, the MAC does not receive the packet. The Host has the option of accepting or ignoring the packet. MCPAS PRMS INVFILT SMSC LAN9420/LAN9420i Ethernet frame (1518 BYTES) SOURCE ADDR. TYPE (6 BYTES) (2 BYTES) (46 - 1500 BYTES) Ethernet frame with VLAN TAG (1522 BYTES) SOURCE ADDR. TPID TYPE TYPE (6 BYTES) ...
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... Pass all multicast frames. Frames with physical addresses are hash- filtered Section 4.4.2, "MAC Address High Section 4.4.3, "MAC Section 125) and multicast hash table low (refer 126) in the MCSR to form a 123) and the MAC address 124). If the SMSC LAN9420/LAN9420i ...
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... Wakeup Frame Filter register (WUFF). structure. Note 3.1 Wakeup frame detection can be performed when LAN9420/LAN9420i is in any power state. Wakeup frame detection is enabled when the WUEN bit is set. Note: When wake-up frame detection is enabled via the WUEN bit of the Register ...
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... FILTER i BYTE MASK DESCRIPTION FILTER i COMMANDS Table 3.17 describes the Filter i Offset bit fields. Table 3.17 Filter i Offset Bit Definitions FILTER i OFFSET DESCRIPTION 58 DATASHEET Datasheet Table 3.16 shows the Filter I command SMSC LAN9420/LAN9420i ...
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... Magic Packet pattern. It checks only packets with the MAC’s address or a broadcast address to meet the Magic Packet requirement. The MAC checks each received frame for the pattern 48’hFF_FF_FF_FF_FF_FF after the destination and source address field. SMSC LAN9420/LAN9420i Table 3.18 Filter i CRC-16 Bit Definitions FILTER i CRC-16 DESCRIPTION is set ...
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... It should be noted that Magic Packet detection can be performed when LAN9420/LAN9420i is in any power management state. 3.5.5 Receive Checksum Offload Engine (RXCOE) The receive checksum offload engine (RXCOE) provides assistance to the Host by calculating a 16- bit checksum for a received Ethernet frame. The RXCOE readily supports the following IEEE802.3 ...
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... Figure 3.21 Ethernet Frame with VLAN Tag {DSAP, SSAP, CTRL, OUI[23:16 DST SRC Figure 3.22 Ethernet Frame with Length Field and SNAP Header SMSC LAN9420/LAN9420i L3 Packet Calculate Checksum Figure 3.20 Type II Ethernet Frame L3 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum 61 DATASHEET F ...
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... Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface {OUI[15:0], PID[15:0 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum Checksum Offload Engine Control Register (COE_CR) (MAC_CR)) and vice versa. These functions cannot be enabled 62 DATASHEET Datasheet enables the SMSC LAN9420/LAN9420i ...
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... Note: The TX checksum cannot be inserted in the MAC header (first 14 bytes the last 4 bytes of the TX packet. 15:12 RESERVED SMSC LAN9420/LAN9420i Table 3.20). The TX checksum preamble instructs the TXCOE on Table 3.20 TX Checksum Preamble DESCRIPTION 63 DATASHEET Revision 1 ...
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... Section 4.4, "MAC Control and Status Registers (MCSR)," on page 118 description of the MCSR. 3.6 10/100 Ethernet PHY LAN9420/LAN9420i integrates an IEEE 802.3 Physical Layer for Twisted Pair Ethernet applications (PHY). The PHY can be configured for either 100 Mbps (100BASE-TX Mbps (10BASE-T) Ethernet operation. The PHY block includes: ...
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... SMSC LAN9420/LAN9420i 100M PLL 4B/5B 25MHz MII by 4 bits Encoder 125 Mbps Serial MLT-3 Tx MLT-3 MLT-3 Converter Driver MLT-3 CAT-5 Figure 3.25 100BASE-TX Data Path Figure 3.25. Each major block is explained below. ...
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... Sent for rising TX_EN Sent for rising TX_EN Sent for falling TX_EN Sent for falling TX_EN Sent for rising TX_ER INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID 66 DATASHEET Datasheet TRANSMITTER INTERPRETATION 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 SMSC LAN9420/LAN9420i ...
Page 67
... Equalizer, Baseline Wander Correction and Clock and Data Recovery The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, SMSC LAN9420/LAN9420i 100M PLL ...
Page 68
... SSD error), RX_ER is asserted and the value 1110b is driven onto the internal receive data bus (RXD) to the MAC. Note that the internal MII’s data valid signal (RX_DV) is not yet asserted when the bad SSD occurs. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 68 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
Page 69
... The output of the SQUELCH goes to the RX10M block where it is validated as Manchester encoded data. The polarity of the signal is also checked. If the polarity is reversed (local TPI+ is connected to TPI- of the remote partner and vice versa), then this is identified and corrected. The reversed condition SMSC LAN9420/LAN9420i 69 DATASHEET ...
Page 70
... The 16 even-numbered pulses, which may be present or absent, contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 70 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
Page 71
... Parallel Detection If LAN9420/LAN9420i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “ ...
Page 72
... If a user plugs in either a direct connect LAN cable cross-over patch cable, as shown in LAN9420/LAN9420i Auto-MDIX PHY is capable of configuring the TPO+/TPO- and TPI+/TPI- twisted pair pins for correct transceiver operation. The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and termination of an Auto-MDIX design ...
Page 73
... Power Management 3.7.1 Overview LA N94 LAN9420/LAN9420i can signal a wake event detection by asserting the nPME pin. The nPME signal can be generated in all states, including (optionally) the D3 SMSC LAN9420/LAN9420i for additional information on this register. In this mode when bit of the PHY Interrupt Source Flag ...
Page 74
... As a result of the nPME assertion by the device, the PCI Host can reconfigure the power management state. This mechanism is used, for example, when LAN9420/LAN9420i is in low power mode and must be restored to a functional state result of the detection of “Wake On LAN” event. The Host can ...
Page 75
... Internally, LAN9420/LAN9420i generates its required clocks with a phase-locked loop (PLL). The LAN9420/LAN9420i reduces its power consumption in the D3 state by disabling its internal PLL and derivative clocks. The 25MHz clock remains operational in all states where power is applied. ...
Page 76
... This transition occurs when VAUXDET is connected to the PCI 3.3Vaux power COLD supply and all power is off (PCInRST=X, PM_STATE=X, VAUXDET=0, PWRGOOD=0) and then 3.3Vaux is applied (PCInRST=0, PM_STATE=X, VAUXDET PWRGOOD=0). LAN9420/LAN9420i detects the application of auxiliary power and asserts its internal power-on reset (POR). POR resets the and Status Register (PCI_PMCSR) the PCI Power Management Control and Status Register (PCI_PMCSR) internal PHY is held in the general-power down state and the device is powered by the PCI 3 ...
Page 77
... Management Control and Status Register (PCI_PMCSR) VAUXDET=X, PWRGOOD=1 Transition Reset (D3RST) occurs during this transition. Refer to Section 3.7.5, "Resets," on page 79 SMSC LAN9420/LAN9420i Section 3.7.6, "Detecting Power Management Events," on page 80 state under the following conditions. State transitions are illustrated in A Power Management State (PM_STATE) (PCI_PMCSR) ...
Page 78
... LAN9420/LAN9420i loses all power and context (to LAN9420/LAN9420i, this appears identical to the G3 state). When VAUXDET=1, LAN9420/LAN9420i is powered from the auxiliary power supply and the auxiliary 3.3Vaux supply remains operational. The device is isolated from the PCI bus and ignores all PCI accesses, as well as PCInRST ...
Page 79
... X TX/RX DMACS X SCSR X Note 3.6 PME logic is reset by PCInRST if LAN9420/LAN9420i is not configured to support D3 wake; PME logic is not reset by PCInRST if LAN9420/LAN9420i is configured to support D3 wake. COLD Note 3.7 Software Reset does not clear control register bits marked as NASR. Note 3.8 If PHY was reset on entry to the D3 was not reset on entry to the D3 Note 3 ...
Page 80
... T10, T11 T5 (D3RST) 3.7.6 Detecting Power Management Events LAN9420/LAN9420i supports the ability to generate PCI wake events using nPME on detection of a Magic Packet, Wakeup Frame or Ethernet link status change (energy detect). A simplified diagram of the wake event detection logic is shown in WOL_EN (PMT_CTRL Register) ...
Page 81
... Management Control Register (PMT_CTRL) 3.7.7 Enabling Link Status Change (Energy Detect) Wake Events The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake event (nPME) on detection of an Ethernet link status change. 1. All transmit and receive operations must be halted: a ...
Page 82
... PCI Power Management Control and Status Register Power Management State (PM_STATE) . Device behavior in this state is described in HOT PME Enable (PME_EN) and/or the 82 DATASHEET Datasheet Power Management Control Register field to 11b (‘D3’ state). The Section 3.7.4.4, "The D3HOT PME Status (PME_STATUS) bits are SMSC LAN9420/LAN9420i ...
Page 83
... Table 4.10, “Standard PCI Header Registers Supported,” on page 150 In the case of BAR3, BA may be either the address of the lower (for little endian access) or upper (for big endian access) 512 byte segment of the 1KB MemSpace. See Mapping on page 27 for details. SMSC LAN9420/LAN9420i Figure 3.3 CSR Double Endian 83 DATASHEET for details. ...
Page 84
... Figure 4.1 LAN9420/LAN9420i CSR Memory Map Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface – – I tro tro tro DATASHEET Datasheet SMSC LAN9420/LAN9420i ...
Page 85
... Unless otherwise noted, do not read from or write to reserved addresses. Register attribute examples: R/W: Can be written. Will return current setting on a read. R/WC: Will return current setting on a read. Writing a one clears the bit. SMSC LAN9420/LAN9420i Table 4.1 Register Bit Types REGISTER BIT DESCRIPTION 85 DATASHEET Revision 1 ...
Page 86
... General Purpose Timer Current Count BUS_CFG System Bus Configuration Register PMT_CTRL Power Management Control RESERVED Reserved for Future Use FREE_RUN Free Run Counter E2P_CMD EEPROM Command Register E2P_DATA EEPROM Data Register RESERVED Reserved for Future Use 86 DATASHEET Datasheet REGISTER NAME SMSC LAN9420/LAN9420i ...
Page 87
... This register contains the device ID and block revision. BITS 31:16 Chip ID. This 16-bit field is used to identify the device model. 15:0 Block Revision. This 16-bit field is used to identify the revision of the Ethernet Subsystem. Note 4.1 Default value is dependent on device revision. SMSC LAN9420/LAN9420i 00C0h Size: 32 bits DESCRIPTION 87 DATASHEET TYPE DEFAULT RO ...
Page 88
... When set high, wake event detection is enabled as an interrupt source. 0 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00C4h Size: 32 bits Section 3.3.1, "Interrupt Controller," on DESCRIPTION 88 DATASHEET Datasheet TYPE DEFAULT R R/W 000b R/W 0b R SMSC LAN9420/LAN9420i ...
Page 89
... Slave Bus Error Interrupt (SBERR_INT) When set, indicates that the PCI Target Interface has detected an error when the Host attempted to access the LAN9420/LAN9420i CSR. The interrupt is cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. To guarantee a clean recovery from a SBERR_INT condition, a software ...
Page 90
... DMA interrupt is cleared by clearing the interrupt source in the DMAC_STATUS DCSR. Writing to this bit has no effect. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION Power (PMT_CTRL). Both WUPS bits must be 90 DATASHEET Datasheet TYPE DEFAULT SMSC LAN9420/LAN9420i ...
Page 91
... Any pending interrupts are then issued new, non-zero value is written to the INT_DEAS field, any subsequent interrupts will obey the new setting. Note: The interrupt de-assertion interval does not apply to the wake interrupt. SMSC LAN9420/LAN9420i 00CCh Size: for more information on the Interrupt Controller. DESCRIPTION 91 ...
Page 92
... GPIO0 – bit 16 GPIO1 – bit 17 GPIO2 – bit 18 15:11 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00D0h Size: 32 bits DESCRIPTION 92 DATASHEET Datasheet TYPE DEFAULT RO - R/W 000b RO - R/W 000b RO - R/W 000b for RO - R/W 000b RO - SMSC LAN9420/LAN9420i ...
Page 93
... Default value is dependent on the state of the GPIO pin. Table 4.3 EEPROM Enable Bit Definitions [22] [21] [20 SMSC LAN9420/LAN9420i DESCRIPTION EEDIO FUNCTION EEDIO GPO3 Reserved GPO3 Reserved TX_EN TX_EN TX_CLK 93 DATASHEET TYPE DEFAULT R/W 000b RO - R/W 00b R/W Note 4.2 EECLK FUNCTION EECLK GPO4 RX_DV GPO4 RX_DV RX_CLK Revision 1 ...
Page 94
... Timer (GPT)," on page 30 Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00D4h Size: Section 3.3.3, "General Purpose Timer (GPT)," DESCRIPTION Section 3.3.3, "General Purpose for more details. 94 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W FFFFh SMSC LAN9420/LAN9420i ...
Page 95
... General Purpose Timer Current Count Register (GPT_CNT) Offset: This register reflects the current value of the general purpose timer. BITS 31:16 RESERVED 15:0 General Purpose Timer Current Count (GPT_CNT) This 16-bit field reflects the current value of the GPT. SMSC LAN9420/LAN9420i 00D8h Size: 32 bits DESCRIPTION 95 DATASHEET TYPE DEFAULT ...
Page 96
... DCSR is cleared. Setting Priority Ratio (RX:TX) ------------------------------------------------ 00b 01b 10b 11b 24:0 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00DCh Size: DESCRIPTION 1:1 2:1 3:1 4:1 96 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 0b R/W 00b RO - SMSC LAN9420/LAN9420i ...
Page 97
... PHY interrupt (Energy-Detect) 1xb – MAC wakeup event (Wakeup Frame or Magic Packet) Note: If waking from a reduced-power state causes the assertion of a device reset, the wakeup status bits will be cleared. 2:0 RESERVED SMSC LAN9420/LAN9420i 00E0h Size: 32 bits DESCRIPTION 97 DATASHEET TYPE ...
Page 98
... Refer to 3.3.4, "Free-Run Counter (FRC)," on page 31 FRC. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00F4h Size: 32 bits DESCRIPTION for more information on the 98 DATASHEET Datasheet TYPE DEFAULT RO - Section SMSC LAN9420/LAN9420i ...
Page 99
... Busy remains busy until the EPC Time-out occurs. At that time the busy bit is cleared. Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address and SSVID/SSID from the EEPROM, the EPC Busy bit is cleared. SMSC LAN9420/LAN9420i 00F8h Size: 32 bits DESCRIPTION 99 DATASHEET ...
Page 100
... WRAL commands are the only EPC commands that will time- out if an EEPROM device is not present -and- the EEDIO signal is pulled low. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION 100 DATASHEET Datasheet TYPE DEFAULT R/W 000b RO - R/WC 0b SMSC LAN9420/LAN9420i ...
Page 101
... MAC address and SSVID/SSID after power-up, or after a RELOAD command has completed. 7:0 EPC Address (EPC_ADDR) The 8-bit value in this field is used by the EEPROM Controller to address the specific memory location in the Serial EEPROM. This is a Byte aligned address. SMSC LAN9420/LAN9420i DESCRIPTION 101 DATASHEET TYPE DEFAULT R/WC ...
Page 102
... EEPROM controller during auto-loading, or the last value read during an attempt to auto- load the EEPROM contents. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00FCh Size: 32 bits DESCRIPTION 102 DATASHEET Datasheet TYPE DEFAULT RO - R/W Note 4.3 SMSC LAN9420/LAN9420i ...
Page 103
... RESERVED 0050h CUR_TX_BUF_ADDR 0054h CUR_RX_BUF_ADDR 0058h – 007Ch RESERVED SMSC LAN9420/LAN9420i SYMBOL Bus Mode Register Transmit Poll Demand Register Receive Poll Demand Register Receive List Base Address Register Transmit List Base Address Register DMA Controller Status Register DMA Controller Control (Operation Mode) Register ...
Page 104
... Note: It will take up to 120ns for the SRST to complete Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0000h Size: 32 bits DESCRIPTION 104 DATASHEET Datasheet TYPE DEFAULT R/W 001000b R/W 0b R/W 00000b R/W 0b R/W/SC 0b SMSC LAN9420/LAN9420i ...
Page 105
... DMAC_STATUS register (transmit buffer unavailable - TU) is not asserted. A write to this register is only effective if the transmit process is in the suspended state. A Read of this register will timeout and invalid data will be returned. SMSC LAN9420/LAN9420i 0004h Size: 32 bits ...
Page 106
... RU) is not set. A write to this register is only effective if the receive process is in the suspended state. A Read of this register will timeout and invalid data will be returned. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0008h Size: 32 bits DESCRIPTION 106 DATASHEET Datasheet TYPE DEFAULT WO - SMSC LAN9420/LAN9420i ...
Page 107
... This field points to the start of the receive buffer descriptor list. The descriptor list resides in the Host memory. Writing this register is only valid when the RX DMA engine is in the stopped state. When stopped, this register must be written before the START command is given. 3:0 RESERVED SMSC LAN9420/LAN9420i 000Ch Size: 32 bits DESCRIPTION 107 ...
Page 108
... TX DMA engine is in the stopped state. When stopped, this register must be written before the START command is given. 3:0 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0010h Size: 32 bits DESCRIPTION 108 DATASHEET Datasheet TYPE DEFAULT R/W 28‘ SMSC LAN9420/LAN9420i ...
Page 109
... This bit is the logical OR of other bits within this register. Only unmasked bits affect this register. Below is the list of bits: DMAC_STATUS[1]: Transmit process stopped (TPS) DMAC_STATUS[7]: Receive buffer unavailable (RU) DMAC_STATUS[8]: Receive process stopped (RPS) SMSC LAN9420/LAN9420i 0014h Size: 32 bits DESCRIPTION DESCRIPTION ...
Page 110
... Indicates that a frame transmission was completed and TDES1[31] is set in the first Descriptor indicating that the TX descriptor has been updated. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION 110 DATASHEET Datasheet TYPE DEFAULT RO - R/WC 0b R/WC 0b R/ R/WC 0b R/WC 0b R/WC 0b SMSC LAN9420/LAN9420i ...
Page 111
... Operate on Second Frame (OSF) When set, this bit instructs the DMA Controller to process a second frame of transmit data even before status for the first frame is obtained. This bit affects the DMA Controller but not the MIL. SMSC LAN9420/LAN9420i 0018h Size: 32 bits DESCRIPTION ...
Page 112
... Receive Process State (RS) as Running and Receive Process Stopped (RPS) does not assert). 0 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION MAC Control Register (MAC_CR)). MAC Control Register 112 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN9420/LAN9420i ...
Page 113
... Interrupt Summary Enable bit (bit [15]) are set. 5 RESERVED 4:3 RESERVED 2 Transmit Buffer Unavailable (TU_EN) The Transmit Buffer Unavailable Interrupt is enabled only when this bit and the Normal Interrupt Summary Enable bit (bit [16]) are set. SMSC LAN9420/LAN9420i 001Ch Size: 32 bits DESCRIPTION 113 DATASHEET TYPE DEFAULT ...
Page 114
... Transmit Interrupt (TI_EN) The Transmit Interrupt is enabled only when this bit and the Normal Interrupt Summary Enable bit (bit [16]) are set. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION 114 DATASHEET Datasheet TYPE DEFAULT R/W 0b R/W 0b SMSC LAN9420/LAN9420i ...
Page 115
... RX Buffer Unavailable Counter (RX_BUFF_UNAV) This field indicates the number of frames missed due to receive buffers being unavailable. This counter is incremented each time the DMAC discards an incoming frame. This counter is automatically cleared on a read. SMSC LAN9420/LAN9420i 0020h Size: 32 bits DESCRIPTION 115 DATASHEET ...
Page 116
... TX_BUFF_ADDR This field contains the pointer to the current buffer address pointer used by the DMAC during TX operation. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0050h Size: 32 bits DESCRIPTION 116 DATASHEET Datasheet TYPE DEFAULT RO 32‘h0 SMSC LAN9420/LAN9420i ...
Page 117
... Current Receive Buffer Address Register (RX_BUFF_ADDR) Offset: This register points to the current receive buffer address being read by the DMAC. BITS 31:0 RX_BUFF_ADDR This field contains the pointer to the current buffer address pointer used by the DMAC during RX operation. SMSC LAN9420/LAN9420i 0054h Size: 32 bits DESCRIPTION 117 DATASHEET TYPE ...
Page 118
... MAC Address Low Multicast Hash Table High Multicast Hash Table Low MII Address MII Data Flow Control VLAN1 Tag VLAN2 Tag Wakeup Frame Filter Wakeup Control and Status Checksum Offload Engine Control Reserved for future use 118 DATASHEET Datasheet REGISTER NAME SMSC LAN9420/LAN9420i ...
Page 119
... When set, the address check Function operates in Inverse filtering mode. This is valid only during Perfect filtering mode. 16 Pass Bad Frames (PASSBAD) When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. SMSC LAN9420/LAN9420i 0080h Size: 32 bits DESCRIPTION 119 ...
Page 120
... RESERVED 13 Hash/Perfect Filtering Mode (HPFILT) When reset (0), LAN9420/LAN9420i will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register ...
Page 121
... Transmitter enable (TXEN) When set, the MAC’s transmitter is enabled and it will transmit frames from the buffer onto the cable. When reset, the MAC’s transmitter is disabled and will not transmit any frames. SMSC LAN9420/LAN9420i DESCRIPTION (Note 4.4) after it detects a collision, where: ...
Page 122
... Receive Process State (RS) as Running and Receive Process Stopped (RPS) does not assert). 1-0 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION prior to enabling the receiver (by setting DMA 122 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN9420/LAN9420i ...
Page 123
... This register contains the upper 16 bits of the physical address of the MAC, where ADDRH[15: the 6 octet of the RX frame. BITS 31:16 RESERVED 15-0 Physical Address [47:32] This field contains the upper 16 bits (47:32) of the physical address of the LAN9420/LAN9420i device. SMSC LAN9420/LAN9420i 0084h Size: 32 bits DESCRIPTION 123 DATASHEET TYPE DEFAULT RO - ...
Page 124
... Size: DESCRIPTION Table 4.6 ADDRL, ADDRH Byte Ordering ORDER OF RECEPTION ON ETHERNET Figure 0xBC 0x9A ADDRH 0x78 0x56 0x34 0x12 ADDRL 124 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 32‘ 4.2. The values required to automatically Section 3.3.5.1, "EEPROM Format," SMSC LAN9420/LAN9420i ...
Page 125
... The Multicast Hash Table Hi register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table. BITS 31-0 Upper 32 bits of the 64-bit Hash Table SMSC LAN9420/LAN9420i 008Ch Size: 32 bits DESCRIPTION 125 ...
Page 126
... Hash Table High Register (HASHH)," on page 125 BITS 31-0 Lower 32 bits of the 64-bit Hash Table Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0090h Size: 32 bits for further details. DESCRIPTION 126 DATASHEET Datasheet Section 4.4.4, TYPE DEFAULT R/W 32‘h0 SMSC LAN9420/LAN9420i ...
Page 127
... The MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The MII data register is invalid until the MAC has cleared this bit during a PHY read operation. SMSC LAN9420/LAN9420i 0094h Size: 32 bits ...
Page 128
... This contains the 16-bit value read from the PHY read operation or the 16- bit data value to be written to the PHY before an MII write operation. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0098h Size: 32 bits DESCRIPTION 128 DATASHEET Datasheet for further details. TYPE DEFAULT RO - R/W 0000h SMSC LAN9420/LAN9420i ...
Page 129
... To initiate a PAUSE control frame, the Host system must set this bit to 1. During a transfer of control frame, this bit continues to be set, signifying that a frame transmission is in progress. After the PAUSE control frame’s transmission is complete, the MAC resets to 0. SMSC LAN9420/LAN9420i 009Ch Size: 32 bits ...
Page 130
... This contains the VLAN Tag field to identify the VLAN1 frames. This field is th compared with the 13 and 14 frame detection. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00A0h Size: 32 bits DESCRIPTION th bytes of the incoming frames for VLAN1 130 DATASHEET Datasheet TYPE DEFAULT RO - R/W FFFFh SMSC LAN9420/LAN9420i ...
Page 131
... RESERVED 15:0 VLAN2 Tag Identifier (VTI2) This contains the VLAN Tag field to identify the VLAN2 frames. This field is th compared with the 13 and 14 frame detection. SMSC LAN9420/LAN9420i 00A4h Size: 32 bits DESCRIPTION th bytes of the incoming frames for VLAN2 131 DATASHEET TYPE ...
Page 132
... WFF may cause the internal read/write pointers to be left in a position other than pointing to the first entry. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00A8h Size: 32 bits DESCRIPTION 132 DATASHEET Datasheet TYPE DEFAULT R/W 0000_0000h SMSC LAN9420/LAN9420i ...
Page 133
... Wakeup Frame Enable (WAKE_EN) When set, remote wakeup mode is enabled and the MAC is capable of detecting wakeup frames as programmed in the Wakeup Frame Filter. 1 Magic Packet Enable (MPEN) When set, Magic Packet wakeup mode is enabled. 0 RESERVED SMSC LAN9420/LAN9420i 00ACh Size: 32 bits DESCRIPTION 133 DATASHEET TYPE ...
Page 134
... These functions cannot be enabled simultaneously. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 00B0h Size: 32 bits DESCRIPTION MAC Control Register (MAC_CR)) 134 DATASHEET Datasheet . TYPE DEFAULT R/W 0b R/W 0b SMSC LAN9420/LAN9420i ...
Page 135
... Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 17 Mode Control/Status Register 18 Special Modes 27 Control / Status Indication Register 29 Interrupt Source Register 30 Interrupt Mask Register 31 PHY Special Control/Status Register SMSC LAN9420/LAN9420i Table 4.7, "PHY Control and Status Registers" REGISTER NAME 135 DATASHEET below. Revision 1.4 (12-17-08) ...
Page 136
... Collision Test 1 = enable COL test disable COL test 6:0 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 0 Size: 16 bits DESCRIPTION 136 DATASHEET Datasheet TYPE DEFAULT R/W/SC 0b R/W 0b R/W 1b R R/W/SC 0b R SMSC LAN9420/LAN9420i ...
Page 137
... Link Status 1 = link is up link is down 1 Jabber Detect 1 = jabber condition detected jabber condition detected 0 Extended Capabilities 1 = supports extended capabilities registers 0 = does not support extended capabilities registers. SMSC LAN9420/LAN9420i 1 Size: 16 bits DESCRIPTION 137 DATASHEET TYPE DEFAULT ...
Page 138
... Index (In Decimal): BITS 15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 2 Size: 16 bits DESCRIPTION 138 DATASHEET Datasheet TYPE DEFAULT R/W 0007h SMSC LAN9420/LAN9420i ...
Page 139
... Index (In Decimal): BITS 15:10 PHY ID Number b Assigned to the 19th through 24th bits of the OUI. 9:4 Model Number Six-bit manufacturer’s model number. 3:0 Revision Number Four-bit manufacturer’s revision number. SMSC LAN9420/LAN9420i 3 Size: 16 bits DESCRIPTION 139 DATASHEET TYPE DEFAULT R/W C0C3h ...
Page 140
... Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 4 Size: 16 bits DESCRIPTION 4.5) 140 DATASHEET Datasheet TYPE DEFAULT R R/W 0b R/W - R/W 00b R/W 0b R/W 1b R/W 1b R/W 1b R/W 1b R/W 00001b SMSC LAN9420/LAN9420i ...
Page 141
... TX with full duplex full duplex ability 7 100BASE- able ability 6 10BASE-T Full Duplex 1 = 10Mbps with full duplex 10Mbps with full duplex ability 5 10BASE 10Mbps able 10Mbps ability 4:0 Selector Field [00001] = IEEE 802.3 SMSC LAN9420/LAN9420i 5 Size: 16 bits DESCRIPTION 141 DATASHEET TYPE DEFAULT ...
Page 142
... Link Partner Auto-Negotiation Able 1 = link partner has auto-negotiation ability 0 = link partner does not have auto-negotiation ability Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 6 Size: 16 bits DESCRIPTION 142 DATASHEET Datasheet TYPE DEFAULT RO - RO/ RO/ SMSC LAN9420/LAN9420i ...
Page 143
... Detect Power-Down is disabled 1=Energy Detect Power-Down is enabled 12:2 RESERVED 1 ENERGYON Indicates whether energy is detected. This bit goes to a “0” valid energy is detected within 256ms. Reset to “1” by hardware reset, unaffected by SW reset. 0 RESERVED SMSC LAN9420/LAN9420i 17 Size: 16 bits DESCRIPTION 143 DATASHEET TYPE DEFAULT RO - ...
Page 144
... CRS is active during Transmit & Receive. 101b Repeater mode. Auto-negotiation enabled. 100BASE-TX Half Duplex is advertised. CRS is active during Receive. 110b RESERVED - Do not set LAN9420/LAN9420i in this mode. 111b All capable. Auto-negotiation enabled. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 18 ...
Page 145
... Receive PLL 10M is locked on the reference clock. In this mode 10M data packets cannot be received. 9:5 RESERVED 4 XPOL Polarity state of the 10BASE-T: 0 – Normal polarity 1 – Reversed polarity 3:0 RESERVED SMSC LAN9420/LAN9420i 27 Size: 16 bits DESCRIPTION 145 DATASHEET TYPE DEFAULT R/W 0b R/W ...
Page 146
... Parallel Detection Fault not source of interrupt 1 INT1 1= Auto-Negotiation Page Received not source of interrupt 0 RESERVED Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 29 Size: 16 bits DESCRIPTION 146 DATASHEET Datasheet TYPE DEFAULT RO - RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/LH 0b RO/ SMSC LAN9420/LAN9420i ...
Page 147
... Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.12 Interrupt Mask Index (In Decimal): BITS 15:8 RESERVED 7:0 Mask Bits 1 = interrupt source is enabled interrupt source is masked SMSC LAN9420/LAN9420i 30 Size: 16 bits DESCRIPTION 147 DATASHEET TYPE DEFAULT RO - R/W 00h Revision 1.4 (12-17-08) ...
Page 148
... RESERVED Note 4.6 Bit 6 of this register must be set to ‘1’ for write operations. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface 31 Size: 16 bits DESCRIPTION 148 DATASHEET Datasheet TYPE DEFAULT Note 4 000b RO - SMSC LAN9420/LAN9420i ...
Page 149
... RESERVED 78h PCI_PMC 7Ch PCI_PMCSR SMSC LAN9420/LAN9420i Section 3.7, "Power Management," on page 73 DESCRIPTION Standard PCI Header Registers (See for details). PCI Power Management Capabilities Register (PCI_PMC) PCI Power Management Control and Status Register (PCI_PMCSR) ...
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... BAR3’s read back value is FFFFFC00h after writing FFFFFFFFh. BAR4’s read back value is FFFFFF01h after writing FFFFFFFFh. Note 4.9 The Subsystem Vendor ID and Subsystem Device ID can be configured by the serial EEPROM EEPROM is connected to LAN9420/LAN9420i, then the default values in the table are used. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface ...
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... This bit is set indicating that LAN9420/LAN9420i is capable asserting nPME from the D0 state Power State Support (D2_SUP) This bit is cleared since LAN9420/LAN9420i does not support the D2 power management state Power State Support (D1_SUP) This bit is cleared since LAN9420/LAN9420i does not support the D1 power management state ...
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... PCI Power Management registers. Note 4.10 The default state of this field is dependant on the setting of the VAUXDET signal as noted in the description. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION 152 DATASHEET Datasheet TYPE DEFAULT RO 010b 01h SMSC LAN9420/LAN9420i ...
Page 153
... PCI reset (PCInRST). In this case, the bit will maintain its setting until cleared with a write, or until assertion of a power-on reset. If PME_EN is cleared, the device will automatically place the PHY into General Power-Down when entering the D3 7:2 RESERVED SMSC LAN9420/LAN9420i 7Ch Size: 32 bits DESCRIPTION bit in this register is set. When this bit is state ...
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... PCI bus; however D[1:0] are ignored and no state change occurs. Note 4.11 The default state of this field is dependant on the setting of the VAUXDET signal as noted in the description. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface DESCRIPTION 154 DATASHEET Datasheet TYPE DEFAULT R/W 00b SMSC LAN9420/LAN9420i ...
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... Note, device signals are NOT 5 volt tolerant. 5.2 Operating Conditions** Supply Voltage (VDD33A, VDD33BIAS, VDD33IO +3.3V +/- 300mV Ambient Operating Temperature in Still Air (T **Proper operation of LAN9420/LAN9420i is guaranteed only within the ranges specified in this section. SMSC LAN9420/LAN9420i (Note 5. +3.6V (Note (Note ) ...
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... Power Consumption This section details the power consumption of LAN9420/LAN9420i as measured during various modes of operation. Power consumption values are provided for both the device-only, and for the device plus Ethernet components. Note: Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink requirements ...
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... Power Dissipation (Device and Ethernet components) Ambient Operating Temperature in Still Air (T 10BASE-T Full Duplex Supply current (VDD33IO, VDD33BIAS, VDD33A) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) Ambient Operating Temperature in Still Air (T SMSC LAN9420/LAN9420i TYPICAL (@ 3.3V) 252 400 ) A 131 ...
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... Note: Power dissipation is determined by temperature, supply voltage, as well as external source/sink current requirements. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface TYPICAL (@ 3.3V MAXIMUM (@ 3.6V) 145 530 690 ) Note 5.5 A 310 700 ) Note 5.5 A Section 5.2, "Operating Conditions**". 158 DATASHEET Datasheet UNIT UNIT SMSC LAN9420/LAN9420i ...
Page 159
... PCI system, or connected to 5V logic without appropriate voltage level translation. Note 5.8 This specification applies to all IPCI type inputs and tri-stated bi-directional PCI pins. Note 5.9 XI can optionally be driven from a 25MHz single-ended clock oscillator. SMSC LAN9420/LAN9420i Table 5.6 I/O Buffer Characteristics MIN TYP MAX -0 ...
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... OS SYMBOL MIN TYP MAX V 2.2 2.5 OUT V 300 420 DS 160 DATASHEET Datasheet UNITS NOTES mVpk Note 5.10 mVpk Note 5.10 102 % Note 5.10 5.0 nS Note 5.10 0.5 nS Note 5. Note 5. 1.4 nS Note 5.12 UNITS NOTES 2.8 V Note 5.13 585 mV SMSC LAN9420/LAN9420i ...
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... Datasheet 5.5 AC Specifications This section contains timing information for non-PCI signals. Note: LAN9420/LAN9420i adheres to the PCI Local Bus Specification revision 3.0. Refer to the Conventional PCI 3.0 Specification for PCI timing details and parameters. 5.5.1 Equivalent Test Load (Non-PCI Signals) Output timing specifications assume the 25pF equivalent test load illustrated in Note: This test load is not applicable to PCI signals ...
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... PCI Clock Timing The following specifies the PCI clock requirements for LAN9420/LAN9420i: 0.5*VDD33IO 0.4*VDD33IO 0.3*VDD33IO SYMBOL DESCRIPTION t PCICLK cycle time cyc t PCICLK high time high t PCICLK low time low - PCICLK slew rate (Note Note 5.14 This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Revision 1 ...
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... Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.7 PCI I/O Timing The following specifies the PCI I/O requirements for LAN9420/LAN9420i: PCICLK PCI OUTPUTS TRI-STATE PCI OUTPUTS PCI INPUTS Table 5.10 PCI I/O Timing Measurement Conditions SYMBOL test V trise ...
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... Note 5.16 PCInRST is asserted and deasserted asynchronously with respect to the PCICLK signal. Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Table 5.11 PCI I/O Timing Values MIN 2 (Note 5.15 (Note 5.15 100 (Note 5.16) 164 DATASHEET Datasheet TYP MAX UNITS SMSC LAN9420/LAN9420i ...
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... Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.8 EEPROM Timing The following specifies the EEPROM timing requirements for LAN9420/LAN9420i: EECS t cshckh EECLK EEDO EEDI EEDI (VERIFY) SYMBOL DESCRIPTION t EECLK Cycle time ckcyc t EECLK High time ckh t EECLK Low time ...
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... Clock Circuit LAN9420/LAN9420i can accept either a 25MHz crystal (preferred 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum. ...
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... Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 6 Package Outline 6.1 128-VTQFP Package Figure 6.1 LAN9420/LAN9420i 128-VTQFP Package Definition SMSC LAN9420/LAN9420i 167 DATASHEET Revision 1.4 (12-17-08) ...
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... E1 are maximum plastic body size dimensions including mold mismatch. 4. The pin 1 identifier may vary, but is always located within the zone indicated. Figure 6.2 LAN9420/LAN9420i 128-VTQFP Recommended PCB Land Pattern Revision 1.4 (12-17-08) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface ...
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... Section 4.4.12, "Wakeup Control and Status Register (WUCSR)," on page 133 Section 5.9, "Clock Circuit," on page 166 SMSC LAN9420/LAN9420i Table 7.1 Customer Revision History All Fixed various typos. Corrected second sentence of step 3: “This is done by setting the EDPWRDOWN bit in the PHY’s Mode Control/Status register.” ...
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... Advertise support for both symmetric PAUSE and Asymmetric PAUSE Added note stating: When both symmetric PAUSE and asymmetric PAUSE support are advertised (value of 11), the device will only be configured to, at most, one of the two settings upon auto- negotiation completion. 170 DATASHEET Datasheet SMSC LAN9420/LAN9420i ...