LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 54

• Manufacturer Part Number: LAN9420I-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420I-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (12-17-08)
3.5.1
3.5.1.1
3.5.2
retransmission and detection of collision frames, as well as an L3 checksum offload engine for transmit
and receive operations.
The MAC can sustain transmission or reception of minimally-sized back-to-back packets at full line
speed with an inter-packet gap (IPG) of 9.6 microseconds for 10 Mbps and 0.96 microseconds for 100
Mbps.
The transmit and receive data paths are separate within the MAC, allowing the highest performance,
especially in full duplex mode.
The MAC includes a control and status register block (MCSR) through which the MAC can be
configured and monitored by the Host. The MCSR are accessible from the Host system via the Target
Interface of the PCIB.
On the backend, the MAC interfaces with the 10/100 PHY through an MII (Media Independent
Interface) port which is internal to LAN9420/LAN9420i. The MCSR also provide a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
Flow Control
The MAC supports full-duplex flow control using the pause operation and control frame.
Full-Duplex Flow Control
The pause operation inhibits data transmission of data frames for a specified period of time. A pause
operation consists of a frame containing the globally assigned multicast address (01-80-C2-00-00-01),
the PAUSE opcode, and a parameter indicating the quantum of slot time (512 bit times) to inhibit data
transmissions. The PAUSE parameter may range from 0 to 65,535 slot times. The Ethernet MAC logic,
on receiving a frame with the reserved multicast address and PAUSE opcode, inhibits data frame
transmissions for the length of time indicated. If a pause request is received while a transmission is in
progress, then the pause will take effect after the transmission is complete. Control frames are received
and processed by the MAC and are passed on.
The MAC also transmits control frames (pause command) under software control. The software driver
requests the MAC to transmit a control frame, and gives the value of the PAUSE time to be used in
the control frame, through the MAC’s FLOW register. The MAC constructs a control frame with the
appropriate values set in all the different fields (as defined in the 802.3x specification) and transmits
the frame (via the PHY). The transmission of the control frame is not affected by the current state of
the Pause timer value that is set because of a recently received control frame. Refer to
"Flow Control Register (FLOW)," on page 129
MAC.
Virtual Local Area Network (VLAN) Support
Virtual Local Area Networks or VLANs, as defined within the IEEE 802.3 standard, provide network
administrators one means of grouping nodes within a larger network into broadcast domains. To
implement a VLAN, four extra bytes are added to the basic Ethernet packet. As shown in
VLAN Frame on page
Type/Length field. The first two bytes of the VLAN tag identify the tag, and by convention are set to
the value 8100h. The last two bytes identify the specific VLAN associated with the packet; they also
provide a priority field.
The MAC supports VLAN-tagged packets. The MAC provides two registers which are used to identify
VLAN-tagged packets. One register should normally be set to the conventional VLAN ID of 8100h. The
other register provides a way of identifying VLAN frames tagged with a proprietary (not 8100h)
identifier. If a packet arrives bearing either of these tags in the two bytes succeeding the Source
Address field, the controller will recognize the packet as a VLAN-tagged packet. In this case, the
controller increases the maximum allowed packet size from 1518 to 1522 bytes (normally the controller
filters packets larger than 1518 bytes). This allows the packet to be received, and then processed by
the application, or to be transmitted on the network.
55, the four bytes are inserted after the Source Address Field and before the
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
54
for more information on enabling flow control in the
SMSC LAN9420/LAN9420i
Section 4.4.8,
Figure 3.18
Datasheet