LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 53

• Manufacturer Part Number: LAN9420I-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420I-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.5
10/100 Ethernet MAC
The Ethernet Media Access Controller (MAC) provides the following features:
The MAC block includes a MAC Interface Layer (MIL). The MIL provides a FIFO interface between the
DMAC and the MAC. The MIL provides the following features:
The MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-
compliant node and provides an interface between the Host system and the internal Ethernet PHY.
The MAC can operate in either 100-Mbps or 10-Mbps mode.
The MAC operates in both half-duplex and full-duplex modes. When operating in half-duplex mode,
the MAC complies fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE standard) and ANSI/IEEE 802.3
standards. When operating in full-duplex mode, the MAC complies with IEEE 802.3x full-duplex
operation standard.
The MAC provides programmable enhanced features designed to minimize Host supervision, bus
utilization, and pre- or post-message processing. These features include the ability to disable retries
after a collision, dynamic FCS (Frame Check Sequence) generation on a frame-by-frame basis,
automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic
Compliant with the IEEE 802.3 and 802.3u specifications
Supports 10-Mbps and 100-Mbps data transfer rates
Transmit and receive message data encapsulation
Framing (frame boundary delimitation, frame synchronization)
Error detection (physical medium transmission errors)
Media access management
Medium allocation (collision detection, except in full-duplex operation)
Contention resolution (collision handling, except in full-duplex operation)
Decoding of control frames (PAUSE command) and disabling the transmitter
Generation of control frames
Internal MII interface for communication with the embedded PHY
Supports Virtual Local Area Network (VLAN) operations
Supports both full- and half-duplex operations
Support of CSMA/CD Protocol for half-duplex Mode
Supports flow control for full-duplex operation
Wake detection logic, which detects Wakeup Frames and Magic Packets
Collision detection and auto retransmission on collisions in Half-Duplex Mode
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Options to insert PAD/CRC32 on transmit
Options to set Automatic Pad stripping in Receive packets
Checksum offload engine for calculation of layer 3 transmit and receive checksum
Provides a bridge between the DMA controller and Ethernet MAC
Separate paths for transmit and receive operations
Separate 2KB FIFOs (one for Transmit and one for Receive operations)
Receive: Sends only filtered packets to DMAC
Transmit: Supports Store and Forward mechanism
Transmit: Frame data held in MIL FIFO until the MAC retransmits the packets without collision
DATASHEET
53
Revision 1.4 (12-17-08)