LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 113

• Manufacturer Part Number: LAN9420I-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420I-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
4.3.8
31:17
13:11
BITS
4:3
16
15
14
10
9
8
7
6
5
2
RESERVED
Normal Interrupt Summary Enable (NIS_EN)
When set, normal interrupt is enabled. When reset, no normal interrupt is
enabled. This bit enables the following bits:
DMAC_STATUS[0]: Transmit interrupt (TI)
DMAC_STATUS[2]: Transmit buffer unavailable (TU)
DMAC_STATUS[6]: Receive interrupt (RI)
Abnormal Interrupt Summary Enable (AIS_EN)
When set, abnormal interrupt is enabled. When reset, no abnormal interrupt
is enabled. This bit enables the following bits:
DMAC_STATUS[1]: Transmit process stopped (TPS)
DMAC_STATUS[5]: RESERVED
DMAC_STATUS[7]: Receive buffer unavailable (RU)
DMAC_STATUS[8]: Receive process stopped (RPS)
RESERVED
RESERVED
RESERVED
Receive Watchdog Timeout (RWT_EN)
The Receive Watchdog Timeout is enabled only when this bit and the
Abnormal Interrupt Summary Enable bit (bit [15]) are set.
Receive Process Stopped (RPS_EN)
The Receive Process Stopped Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
Receive Buffer Unavailable (RU_EN)
The Receive Buffer Unavailable Interrupt is enabled only when this bit and
the Abnormal Interrupt Summary Enable bit (bit [15]) are set.
Receive Interrupt (RI_EN)
The Receive Interrupt is enabled only when this bit and the Abnormal
Interrupt Summary Enable bit (bit [15]) are set.
RESERVED
RESERVED
Transmit Buffer Unavailable (TU_EN)
The Transmit Buffer Unavailable Interrupt is enabled only when this bit and
the Normal Interrupt Summary Enable bit (bit [16]) are set.
DMA Controller Interrupt Enable Register (DMAC_INTR_ENA)
This register enables the DMAC interrupts reported in the DMAC_STATUS register. Setting a bit to 1
enables the corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Offset:
DESCRIPTION
001Ch
DATASHEET
113
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Revision 1.4 (12-17-08)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
-
-
-