LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 122

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LAN9420I-NU

Manufacturer Part Number
LAN9420I-NU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LAN9420I-NU

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Compliant

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Revision 1.4 (12-17-08)
BITS
1-0
2
Receiver Enable (RXEN)
When set (1), the MAC’s receiver is enabled and will receive frames from
the internal PHY. When reset, the MAC’s receiver is disabled and will not
receive any frames from the internal PHY.
Note:
Note:
RESERVED
In order to successfully enable the receive path, the RX DMAC
must be enabled by setting the Start/Stop Receive bit (SR) bit of
the
(DMAC_CONTROL)
RXEN).
In order to successfully disable the receive path, the receiver must
be disabled (by clearing RXEN) prior to disabling the RX DMAC
(by clearing the Start/Stop Receive bit (SR) bit of the
Controller Control (Operation Mode) Register
(DMAC_CONTROL)). Otherwise, RX DMA will not stop
(DMAC_STATUS will continue to show the Receive Process State
(RS) as Running and Receive Process Stopped (RPS) does not
assert).
DMA Controller Control (Operation Mode) Register
DESCRIPTION
prior to enabling the receiver (by setting
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
122
DMA
TYPE
SMSC LAN9420/LAN9420i
R/W
RO
DEFAULT
Datasheet
0b
-

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