LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 120

• Manufacturer Part Number: LAN9420I-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420I-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (12-17-08)
BITS
15
14
13
12
11
10
9
8
Hash Only Filtering mode (HO)
When set, the address check Function operates in the imperfect address
filtering mode both for physical and multicast addresses
RESERVED
Hash/Perfect Filtering Mode (HPFILT)
When reset (0), LAN9420/LAN9420i will implement a perfect address filter
on incoming frames according the address specified in the MAC address
register.
When set (1), the address check function does imperfect address filtering
of multicast incoming frames according to the hash table specified in the
multicast hash table register.
If the Hash Only Filtering mode (HO) bit is set (1), then the physical (IA)
are imperfect filtered too. If the Hash Only Filtering mode (HO) bit is reset
(0), then the IA addresses are perfect address filtered according to the MAC
Address register.
Late Collision Control (LCOLL)
When set, enables retransmission of the collided frame even after the
collision period (late collision). When reset, the MAC disables frame
transmission on a late collision. In any case, the Late Collision status is
appropriately updated in the Transmit Packet status.
Disable Broadcast Frames (BCAST)
When set, disables the reception of broadcast frames. When reset,
forwards all broadcast frames to the application.
Note:
Disable Retry (DISRTY)
When set, the MAC attempts only one transmission. When a collision is
seen on the bus, the MAC ignores the current frame and goes to the next
frame and a retry error is reported in the Transmit status. When reset, the
MAC attempts 16 transmissions before signaling a retry error.
RESERVED
Automatic Pad Stripping (PADSTR)
When set, the MAC strips the pad field on all incoming frames, if the length
field is less than 46 bytes. The FCS field is also stripped, since it is
computed at the transmitting station based on the data and pad field
characters, and is invalid for a received frame that has had the pad
characters stripped. Receive frames with a 46-byte or greater length field
are passed to the Application unmodified (FCS is not stripped). When reset,
the MAC passes all incoming frames to Host memory unmodified.
Note:
When wake-up frame detection is enabled via the WUEN bit of the
Wakeup Control and Status Register
wake-up frame will wake-up the device despite the state of this bit.
When PADSTR is enabled, the RX Checksum Offload Engine
must be disabled (RX_COE_EN bit of the
Engine Control Register
functions cannot be enabled simultaneously.
DESCRIPTION
(COE_CR)) and vice versa. These
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
120
(WUCSR), a broadcast
Checksum Offload
TYPE
SMSC LAN9420/LAN9420i
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
DEFAULT
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