LAN9420I-NU Standard Microsystems (SMSC), LAN9420I-NU Datasheet - Page 78

• Manufacturer Part Number: LAN9420I-NU
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9420I-NU

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (12-17-08)
3.7.4.5
3.7.4.5.1
3.7.4.5.2
The D3
LAN9420/LAN9420i’s behavior in this state is dependant on the status of VAUXDET. When
VAUXDET=0, LAN9420/LAN9420i is powered from the system’s +3.3V supply; wake from D3
disabled and the PCI +3.3V power supply is off. Since VAUXDET=0, the device is powered from the
system’s +3.3V power supply and LAN9420/LAN9420i loses all power and context (to
LAN9420/LAN9420i, this appears identical to the G3 state).
When VAUXDET=1, LAN9420/LAN9420i is powered from the auxiliary power supply and the auxiliary
3.3Vaux supply remains operational. The device is isolated from the PCI bus and ignores all PCI
accesses, as well as PCInRST. If the
Control and Status Register (PCI_PMCSR)
a wake event from D3
and transmit operation is disabled. In D3
derivative clocks.
POWER MANAGEMENT EVENTS IN D3
If configured to do so, the device is capable of detecting MAC (WOL, Magic Packet) and PHY (link
status change) wake events and is capable of asserting nPME as a result of detection. In order to
generate nPME in the D3
supply.
EXITING THE D3
The device will exit the D3
Figure 3.28 on page
D3
(PCInRST=1 to 0, PM_STATE=11b, VAUXDET=X, PWRGOOD=1). Refer to
"Resets," on page 79
D3
PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
D3
= 1, this means that the 3.3Vaux supply was active and PCI power is now turned on (PCInRST=1
to 0, PM_STATE=11b, VAUXDET=1, PWRGOOD=0 to 1). In this case the entire device is reset,
with the exception of the PCI PME context, which is preserved. The internal PHY is reset and is
configured for all capable operation with auto negotiation enabled.
If VAUXDET = 0, the device is seeing power for the first time and the internal power-on reset (POR)
is asserted (PCInRST=1 to 0, PM_STATE=X, VAUXDET=0, PWRGOOD=0 to 1). All logic and
registers are reset and the internal PHY is configured for all capable operation with auto negotiation
enabled.
D3
PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
HOT
HOT
COLD
COLD
COLD
to D0
to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X,
to D0
to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X,
State
U
U
COLD
(T8): This transition occurs when PCInRST is asserted while in the D3
(T9): This transition occurs when the +3.3V power supply is turned on. If VAUXDET
75.
COLD
STATE
to for more information on this reset.
COLD
COLD
. In this state the PCI 3.3Vaux power is on, but normal Ethernet receive
state, LAN9420/LAN9420i must be powered from the 3.3Vaux power
state under the following conditions. State transitions are illustrated in
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
PME Enable (PME_EN)
COLD
COLD
78
is set, it is assumed that the device is configured to detect
power is reduced by disabling the internal PLL and
bit in the
PCI Power Management
SMSC LAN9420/LAN9420i
Section 3.7.5,
HOT
Datasheet
state
COLD
is