OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 285

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
20.5.3.4 Application Interrupt and Reset Control Register
Table 248. ICSR bit assignments
[1]
[2]
When you write to the ICSR, the effect is Unpredictable if you:
The AIRCR provides endian status for data accesses and reset control of the system. See
the register summary in
To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are:
Bits
[25]
[24:23]
[22]
[21:18]
[17:12]
[11:6]
[5:0]
•
•
This is the same value as IPSR bits[5:0], see
The NMI is not implemented on the EM773.
write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
Name
PENDSTCLR
-
ISRPENDING
-
VECTPENDING
-
VECTACTIVE
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
[1]
Table 20–246
RO
-
Type
WO
-
RO
-
RO
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
Function
SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick
exception.
This bit is WO. On a register read its value is Unknown.
Reserved.
Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
Reserved.
Indicates the exception number of the highest priority
pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
Reserved.
Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
active exception.
Remark: Subtract 16 from this value to obtain the
CMSIS IRQ number that identifies the corresponding bit
in the Interrupt Clear-Enable, Set-Enable,
Clear-Pending, Set-pending, and Priority Register, see
Table
and
Table
20–220.
Table 20–249
20–220.
for its attributes.
[1]
UM10415
of the currently
© NXP B.V. 2010. All rights reserved.
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