OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 173
![BOARD EVAL EM773 METER US PLUG](/photos/38/74/387430/om13005_sml.jpg)
OM13005,598
Manufacturer Part Number
OM13005,598
Description
BOARD EVAL EM773 METER US PLUG
Manufacturer
NXP Semiconductors
Type
Other Power Managementr
Specifications of OM13005,598
Design Resources
Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
Main Purpose
Power Management, Energy/Power Meter
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
EM773FHN33,551
Interface Type
USB
Maximum Operating Temperature
+ 150 C
Operating Supply Voltage
1.8 V to 3.6 V
Product
Power Management Development Tools
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
EM773, OL2381
Other names
568-6680
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NXP Semiconductors
Table 164: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C)
Table 165. External match control
UM10415
User manual
Bit
0
1
2
3
5:4
7:6
9:8
11:10
31:12
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Symbol
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
EMC3
-
bit description
13.8.11 Count Control Register (TMR32B0CTCR and TMR32B1TCR)
00
01
10
11
Description
External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of
this output. This bit is driven to the CT32B0_MAT0 pins if the match function is selected in
the IOCON registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of
this output. This bit is driven to the CT32B0_MAT1 pins if the match function is selected in
the IOCON registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of
this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit can
either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of
this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match Control 0. Determines the functionality of External Match 0.
shows the encoding of these bits.
External Match Control 1. Determines the functionality of External Match 1.
shows the encoding of these bits.
External Match Control 2. Determines the functionality of External Match 2.
shows the encoding of these bits.
External Match Control 3. Determines the functionality of External Match 3.
shows the encoding of these bits.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Chapter 13: EM773 32-bit counter/timers (CT32B0/1)
Table 165
Table 165
Table 165
Table 165
UM10415
© NXP B.V. 2010. All rights reserved.
Reset
value
0
0
0
0
00
00
00
00
NA
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