OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 280

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
Fig 64. IPR register
20.5.2.5 Interrupt Clear-pending Register
20.5.2.6 Interrupt Priority Registers
IPR7
IPR
IPR0
31
The ICPR removes the pending state from interrupts, and shows which interrupts are
pending. See the register summary in
The bit assignments are:
Table 243. ICPR bit assignments
Remark: Writing 1 to an ICPR bit does not affect the active state of the corresponding
interrupt.
The IPR0-IPR7 registers provide an 2-bit priority field for each interrupt. These registers
are only word-accessible. See the register summary in
Each register holds four priority fields as shown:
Table 244. IPR bit assignments
Bits
[31:0]
Bits
[31:24]
[23:16]
[15:8]
[7:0]
PRI_(4n+3)
•
PRI_31
PRI_3
a disabled interrupt sets the state of that interrupt to pending.
Name
Priority, byte offset 3
Priority, byte offset 2
Priority, byte offset 1
Priority, byte offset 0
24 23
All information provided in this document is subject to legal disclaimers.
Name
CLRPEND
Rev. 1 — 10 September 2010
PRI_(4n+2)
PRI_30
PRI_2
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
Function
Each priority field holds a priority value, 0-3. The lower the
value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:6] of each field, bits
[5:0] read as zero and ignore writes.
16 15
Function
Interrupt clear-pending bits.
Write:
0 = no effect
1 = removes pending state an interrupt.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
Table 20–238
PRI_(4n+1)
PRI_29
PRI_1
for the register attributes.
Table 20–238
8 7
PRI_(4n)
PRI_28
PRI_0
for their attributes.
UM10415
© NXP B.V. 2010. All rights reserved.
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