OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 246

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
Table 227. Cortex-M0 instructions
UM10415
User manual
Mnemonic
ADCS
ADD{S}
ADR
ANDS
ASRS
B{cc}
BICS
BKPT
BL
BLX
BX
CMN
CMP
CPSID
CPSIE
DMB
DSB
EORS
ISB
LDM
LDR
LDR
LDRB
LDRH
LDRSB
LDRSH
LSLS
U
MOV{S}
MRS
MSR
MULS
MVNS
Operands
{Rd,} Rn, Rm
{Rd,} Rn, <Rm|#imm>
Rd, label
{Rd,} Rn, Rm
{Rd,} Rm, <Rs|#imm>
label
{Rd,} Rn, Rm
#imm
label
Rm
Rm
Rn, Rm
Rn, <Rm|#imm>
i
i
-
-
{Rd,} Rn, Rm
-
Rn{!}, reglist
Rt, label
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
{Rd,} Rn, <Rs|#imm>
{Rd,} Rn, <Rs|#imm>
Rd, Rm
Rd, spec_reg
spec_reg, Rm
Rd, Rn, Rm
Rd, Rm
For more information on the instructions and operands, see the instruction descriptions.
•
•
•
angle brackets, <>, enclose alternative forms of the operand
braces, {}, enclose optional operands and mnemonic parts
the Operands column is not exhaustive.
All information provided in this document is subject to legal disclaimers.
Brief description
Add with Carry
Add
PC-relative Address to Register
Bitwise AND
Arithmetic Shift Right
Branch {conditionally}
Bit Clear
Breakpoint
Branch with Link
Branch indirect with Link
Branch indirect
Compare Negative
Compare
Change Processor State, Disable
Interrupts
Change Processor State, Enable
Interrupts
Data Memory Barrier
Data Synchronization Barrier
Exclusive OR
Instruction Synchronization Barrier
Load Multiple registers, increment after
Load Register from PC-relative address -
Load Register with word
Load Register with byte
Load Register with halfword
Load Register with signed byte
Load Register with signed halfword
Logical Shift Left
Logical Shift Right
Move
Move to general register from special
register
Move to special register from general
register
Multiply, 32-bit result
Bitwise NOT
Rev. 1 — 10 September 2010
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
Flags
N,Z,C,V
N,Z,C,V
-
N,Z
N,Z,C
-
N,Z
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
N,Z
-
-
-
-
-
-
-
N,Z,C
N,Z,C
N,Z
-
N,Z,C,V
N,Z
N,Z
Reference
Section 20–20.4.5.1
Section 20–20.4.5.1
Section 20–20.4.4.1
Section 20–20.4.5.1
Section 20–20.4.5.3
Section 20–20.4.6.1
Section 20–20.4.5.2
Section 20–20.4.7.1
Section 20–20.4.6.1
Section 20–20.4.6.1
Section 20–20.4.6.1
Section 20–20.4.5.4
Section 20–20.4.5.4
Section 20–20.4.7.2
Section 20–20.4.7.2
Section 20–20.4.7.3
Section 20–20.4.7.4
Section 20–20.4.5.2
Section 20–20.4.7.5
Section 20–20.4.4.5
Section 20–20.4.4
Section 20–20.4.4
Section 20–20.4.4
Section 20–20.4.4
Section 20–20.4.4
Section 20–20.4.4
Section 20–20.4.5.3
Section 20–20.4.5.3
Section 20–20.4.5.5
Section 20–20.4.7.6
Section 20–20.4.7.7
Section 20–20.4.5.6
Section 20–20.4.5.5
UM10415
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