OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 21

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
3.4.18 WDT clock source update enable register
3.4.19 WDT clock divider register
3.4.20 CLKOUT clock source select register
Table 20.
This register updates the clock source of the watchdog timer with the new input clock after
the WDTCLKSEL register has been written to. In order for the update to take effect at the
input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
a one to WDTCLKUEN.
Table 21.
This register determines the divider values for the watchdog clock wdt_clk.
Table 22.
This register configures the clkout_clk signal to be output on the CLKOUT pin. All three
oscillators and the main clock can be selected for the clkout_clk clock.
The CLKOUTCLKUEN register (see
for the update to take effect.
Bit
1:0
31:2
Bit
0
31:1
Bit
7:0
31:8
Symbol
SEL
-
Symbol
ENA
-
Symbol
DIV
-
WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit
description
WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)
bit description
WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description
All information provided in this document is subject to legal disclaimers.
Value
00
01
10
11
-
Value
0
1
to
255
-
Value
0
1
-
Rev. 1 — 10 September 2010
Description
WDT clock source
IRC oscillator
Main clock
Watchdog oscillator
Reserved
Reserved
Description
WDT clock divider values
Disable
Divide by 1
...
Divide by 255
Reserved
Description
Enable WDT clock source update
No change
Update clock source
Reserved
Section
3.4.21) must be toggled from LOW to HIGH
Chapter 3: EM773 System configuration
UM10415
© NXP B.V. 2010. All rights reserved.
Reset value
0x0
0x00
Reset
value
0x00
0x00
Reset
value
0x00
0x00
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