IP-CPRI Altera, IP-CPRI Datasheet - Page 93

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Signals
CPRI MAP Interface Signals
Table 5–9. CPRI MII Transmitter Interface Signals
CPRI MAP Interface Signals
Table 5–10. CPRI MAP Receiver Interface Signals (Part 1 of 2)
May 2011 Altera Corporation
cpri_mii_txclk
cpri_mii_txen
cpri_mii_txer
cpri_mii_txd[3:0]
cpri_mii_txrd
map{23…0}_rx_clk
map{23…0}_rx_reset
Signal
CPRI MII Interface Transmitter Signals
CPRI MAP Receiver Signals
f
Signal
Table 5–9
you exclude the MAC block from the CPRI IP core.
Table 5–10
the CPRI IP core. The CPRI MAP interfaces are implemented as Avalon-ST interfaces.
Refer to the
Table 5–10
Output
Input
Input
Input
Output
Direction
lists the CPRI MII interface transmitter signals. These signals are available if
and
lists the CPRI MAP receiver interface signals.
Avalon Interface Specifications
Clocks the MII transmitter interface. The cpri_clkout clock drives this signal.
Valid signal from the external Ethernet block, indicating the presence of valid data on
cpri_mii_txd[3:0]. This signal is also asserted while the CPRI MII interface
transmitter block inserts J and K nibbles in the data stream to form the start-of-packet
symbol. This signal is typically asserted one cycle after cpri_mii_txrd is asserted.
After that first cycle following the assertion of cpri_mii_txrd, if cpri_mii_txen is not yet
asserted, the CPRI MII transmitter module inserts Idle cycles until the first cycle in
which cpri_mii_txen is asserted. If cpri_mii_txen is asserted and subsequently
deasserted while cpri_mii_txrd remains asserted, the CPRI MII transmitter module
inserts the end-of-packet sequence.
Ethernet transmit coding error. When this signal is asserted, the CPRI IP core inserts
an Ethernet HALT symbol in the data it passes to the CPRI link.
Ethernet transmit nibble data. The data transmitted from the external Ethernet block to
the CPRI IP core, for transmission on the CPRI link. This input bus is synchronous to
the rising edge of the cpri_clkout clock.
Ethernet read request. Indicates that the MII interface block is ready to read data on
cpri_mii_txd[3:0]. Valid data is recognized 2 cpri_mii_txclk cycles after
cpri_mii_txen is asserted in response to cpri_mii_txrd. The cpri_mii_txrd
signal remains asserted for 2 cpri_mii_txclk cycles following deassertion of
cpri_mii_txen. Deasserting cpri_mii_txrd while cpri_mii_txen is still
asserted backpressures the external Ethernet block.
Table 5–11
Direction
Input
Input
Clock signal for each antenna-carrier interface.
Reset signal for each antenna-carrier interface. This reset is associated
with the mapN_rx_clk clock.
mapN_rx_reset can be asserted asynchronously, but must stay
asserted at least one mapN_rx_clk cycle and must be deasserted
synchronously with mapN_rx_clk. Refer to
for a circuit that shows how to enforce synchronous deassertion of a
reset signal.
list the signals used by the CPRI MAP interface modules of
for details about the Avalon-ST interface.
Description
Description
CPRI MegaCore Function User Guide
Figure 4–8 on page 4–14
5–7