IP-CPRI Altera, IP-CPRI Datasheet - Page 41

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Physical Layer
Figure 4–9. Physical Layer High Level Block Diagram
May 2011 Altera Corporation
Low-Level
Transmitter
Payload
Module
AUX IF
Physical Layer Architecture
Low-level Interface Receiver
Loop
Data
CPRI_TX_MAP
■
■
■
■
Figure 4–9
Transmitter Transceiver
The receiver in the low-level interface receives the input from the CPRI interface, and
performs the following tasks:
■
■
■
Payload
Tx State Machine
I/Q
Transmitter and receiver with the following features:
■
■
■
■
■
■
So
Error reporting
Clock decoupling
Converts the data to the main clock domain
Performs CPRI frame detection, supporting autorate negotiation
Separates data and control words
tx_dataout
CPRI Link
ftware interface (status and control registers)
MUX
High-speed data serialization and deserialization
Clock and data recovery (receiver)
8B/10B encoding and decoding
Frame and control word assembly and delineation
Error detection
Deterministic latency
ETH_TX
Ethernet
Encode
shows the architecture of the physical layer.
HDLC_TX
Bit-Destuff
HDLC
VSS/L1
CPU IF
Module
Low-Level
Receiver
Module
AUX IF
Payload
Timing
CPRI_RX_MAP
Payload
I/Q
RFN + HFN
Recovery
Timing
Receiver Transceiver
Rx State Machine
Frame Alignment
Elastic Buffer
CPRI Link
rx_datain
DEMUX
and
Rx
CPRI MegaCore Function User Guide
Ethernet
ETH_RX
Decode
HDLC_RX
Bit-Destuff
HDLC
VSS/L1/
Alarms
CPU IF
Module
4–17