IP-CPRI Altera, IP-CPRI Datasheet - Page 91

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Signals
CPU Interface Signals
CPU Interface Signals
Table 5–7. CPU Interface Signals (Part 1 of 2)
May 2011 Altera Corporation
cpu_clk
cpu_reset
cpu_irq
cpu_irq_vector[4:0]
cpu_address[13:0]
cpu_write
cpu_read
cpu_byteenable[3:0]
cpu_writedata[31:0]
Signal
f
f
1
You must configure the dynamic reconfiguration block in any CPRI design that
targets an Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX device.
For more information about the transceiver reconfiguration block and about offset
cancellation, refer to the appropriate device handbook.
Table 5–7
an Avalon-MM interface.
Refer to the
Input
Input
Output
Output
Input
Input
Input
Input
Input
Direction
lists the CPU interface module signals. The CPU interface is implemented as
Avalon Interface Specifications
CPU clock signal.
CPU peripheral reset. This reset is associated with the cpu_clk clock.
cpu_reset can be asserted asynchronously, but must stay asserted at least
one cpu_clk cycle and must be de-asserted synchronously with cpu_clk.
Refer to
synchronous deassertion of a reset signal.
Merged CPU interrupt indicator. This signal is the OR of all the bits in the
vector cpu_irq_vector.
This vector contains the following interrupt bits:
CPU word address. Corresponds to bits [15:2] of a byte address with LSBs
2’b00. If you connect an Avalon-MM interface to the CPU interface, connect
bits [15:2] of the incoming Avalon-MM address to cpu_address.
CPU write request.
CPU read request.
CPU data byteenable signal. Enables specific byte lanes during transfers on
ports of width less than 32 bits. Each bit in the cpu_byteenable signal
corresponds to a byte lane in cpu_writedata and cpu_readdata. The least
significant bit of cpu_byteenable corresponds to the lowest byte of each
data bus. The bit value 1 indicates an enabled byte lane, and the bit value 0
indicates a disabled byte lane. Enabled byte lanes must be adjacent: valid
values of cpu_byteenable include only a single sequence of 1’s.
For more information, refer to the definition of the byteenable signal in the
Avalon-MM specification in the
CPU write data.
[4]
[3]
[2]
[1]
[0]
cpu_irq_cpri: Interrupt bit from CPRI_INTR register. This signal is
the OR of all three interrupt bits in the CPRI_INTR register.
cpu_irq_eth_rx: Interrupt from the Ethernet receiver module.
cpu_irq_eth_tx: Interrupt from the Ethernet transmitter module.
cpu_irq_hdlc_rx: Interrupt from the HDLC receiver module.
cpu_irq_hdlc_tx: Interrupt from the HDLC transmitter module.
Figure 4–8 on page 4–14
for details about the Avalon-MM interface.
Avalon Interface
Description
for a circuit that shows how to enforce
CPRI MegaCore Function User Guide
Specifications.
5–5