IP-CPRI Altera, IP-CPRI Datasheet - Page 62

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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Delay Measurement
CPRI MegaCore Function User Guide
following data and synchronization lines on the AUX interface to enable the required
precise frame timing:
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■
■
■
■
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In response to the rising edge of its cpri_tx_sync_rfp input signal, a CPRI REC
master IP core resets the frame synchronization machine. The rising edge of the
cpri_tx_sync_rfp signal must be synchronous with the cpri_clkout clock. On the
seventh cpri_clkout cycle following a cpri_tx_sync_rfp pulse, the cpri_tx_hfp and
cpri_tx_rfp signals pulse, the cpri_tx_x and cpri_tx_hfn signals have the value 0,
and the cpri_tx_bfn signal increments from its previous value.
For more information about the relationships between the synchronization pulses and
numbers, refer to
AUX interface and the CPRI link, refer to
The cpri_tx_aux_data and cpri_tx_aux_mask signals are fields of the
aux_tx_mask_data bus. The other signals described in the preceding list are fields of
the aux_tx_status_data bus. For additional information about the AUX transmitter
signals, refer to
For system configuration and correct synchronization, the CPRI IP core must meet the
CPRI V4.1 Specification measurement and delay requirements. The CPRI IP core
makes the current Rx delay measurement values available in the CPRI_RX_DELAY and
CPRI_EX_DELAY_STATUS delay registers, and makes the round-trip delay measurement
available in the CPRI_ROUND_DELAY register. In addition, the CPRI IP core allows you to
specify settings that control the degree of delay accuracy in the status registers, by
programming the CPRI_RX_DELAY_CTRL and CPRI_EX_DELAY_CONFIG registers.
The following sections describe the delay requirements and how you can use these
registers to ensure that your application conforms to the CPRI V4.1 Specification
delay requirements.
cpri_tx_start—asserted for the duration of the first basic frame following the
offset defined in the CPRI_START_OFFSET_TX register
cpri_tx_rfp and cpri_tx_hfp—synchronization pulses for start of 10 ms radio
frame and start of hyperframe
cpri_tx_bfn and cpri_tx_hfn—current radio frame and hyperframe numbers
cpri_tx_x—index number of the current basic frame in the current hyperframe
cpri_tx_seq—index number of the current 32-bit word in the current basic frame
cpri_tx_aux_data—incoming data port for data on the AUX link
cpri_tx_aux_mask—incoming bit mask for AUX link data that indicates bits that
must be transmitted without changes to the CPRI link
The CPRI IP core layer 1 uses the cpri_tx_aux_mask to select the enabled bit
values in the control transmit table. You must deassert all the mask bits during
K28.5 character insertion in the outgoing CPRI frame (which occurs when Z=X=0).
Otherwise, the CPRI IP core asserts an error signal cpri_tx_error on the
following cpri_clkout clock cycle to indicate that the K28.5 character expected by
the CPRI link protocol has been overwritten.
Table 5–13 on page
Figure 4–16 on page
5–12.
4–35. For the mapping of data between the
Figure 4–17 on page
Chapter 4: Functional Description
4–35.
May 2011 Altera Corporation
Delay Measurement