IP-CPRI Altera, IP-CPRI Datasheet - Page 45

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Physical Layer
May 2011 Altera Corporation
Autorate Negotiation
Low-Level Interface Transmitter
The autorate negotiation feature allows the CPRI IP core to determine the CPRI line
rate at startup dynamically, by stepping down to successively slower line rates if the
low-level receiver cannot achieve frame synchronization with the current line rate. If
you enable the autorate negotiation feature, you can provide dynamic input to the
low-level CPRI interface receiver to implement this capability in your design, using
logic you implement outside the CPRI IP core.
To use this feature, you must include additional external logic in your design.
Appendix B, Implementing CPRI Link Autorate Negotiation
logic required to implement autorate negotiation in your design.
If you configure your CPRI IP core for autorate negotiation, the IP core includes two
output status signals and a register to collect the status information, as well as the
internal support to change CPRI line rate according to your design’s input to the
transceiver dynamic reconfiguration block. In Cyclone IV GX designs, the external
logic must also provide line rate information to the ALTPLL_RECONFIG
megafunction connected to the transceiver.
The transmitter in the low-level interface transmits output to the CPRI interface. This
module performs the following tasks:
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A control transmit table contains an entry for each of the 256 control words in the
current hyperframe. Each control transmit table entry contains a control byte field and
an enabled bit. As the frame is created, if a control word entry is enabled, and the
global tx_ctrl_insert_en bit in the CPRI_CONTROL register is set, the low-level
transmitter writes the control byte to each of the bytes in the frame’s control word. To
write a control byte in the control transmit table, write the frame number X to the
CPRI_CTRL_INDEX register and then write the next intended #Z.X.0 control byte in the
CPRI_TX_CTRL register.
Assembles data and control words in proper output format
Transmits standard frame sequence
Optionally scrambles the outgoing data transmission at 4195.2 Mbps and
6144.0 Mbps CPRI line rates
Inserts the following control words in their appropriate locations in the outgoing
hyperframe:
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Synchronization control byte (K28.5) and filler bytes (D16.2) in the
synchronization control word
Hyperframe number (HFN)
Basic frame number (BFN)
HDLC bit rate
Pointer to start of Ethernet data in current frame
4B/5B-encoded fast C&M Ethernet frames
Bit-stuffed slow C&M HDLC frames
Enabled control transmit table entries
CPRI MegaCore Function User Guide
describes the external
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