IP-CPRI Altera, IP-CPRI Datasheet - Page 139

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

May 2011 Altera Corporation
This appendix describes the most basic initialization sequence for an Altera CPRI IP
core.
To initialize the CPRI IP core, follow these steps:
1. To configure the Altera FPGA with your design, download your .sof file to the
2. Perform the following two actions simultaneously:
3. Write the value 0x21 to the CPRI_CONFIG register (0x8). This CPRI_CONFIG register
4. Observe the cpri_rx_state output signal as it transitions from value 0x0 to value
5. Observe the cpri_rx_hfn_state output signal as it transitions to value 1. When it
6. Observe the cpri_rx_bfn_state output signal as it transitions to value 1. When it
The CPRI IP core can now receive and transmit data on the CPRI link, on the
antenna-carrier interfaces, and on the auxiliary AUX interface.
To access the registers, the system requires an Avalon-MM master, for example a
Nios II processor. The Avalon-MM master can program these registers.
FPGA.
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setting enables the CPRI IP core to start sending K28.5 symbols on the CPRI link.
0x2 to value 0x3. When it has value 0x3, and the cpri_rx_cnt_sync output signal
has value 0x1, the CPRI IP core CPRI receiver interface is in the HFNSYNC2 state.
The cpri_rx_state output signal appears on extended_rx_status_data[1:0] and
the cpri_rx_cnt_sync output signal appears on extended_rx_status_data[4:2].
has value 1, the hyperframe number is initialized. The cpri_rx_hfn_state output
signal appears on extended_rx_status_data[7].
has value 1, the basic frame number is initialized. The cpri_rx_bfn_state output
signal appears on extended_rx_status_data[6].
Perform a global CPRI IP core reset by asserting the following reset signals
simultaneously, holding them asserted for at least three cycles of the slowest
associated clock, and deasserting each as soon as possible thereafter:
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To reset, power down, and power back up the high-speed transceiver, assert
the gxb_powerdown signal.
config_reset
cpu_reset
reset
reset_ex_delay
mapN_rx_reset, for the appropriate values of N
mapN_tx_reset, for the appropriate values of N
A. Initialization Sequence
CPRI MegaCore Function User Guide