IP-CPRI Altera, IP-CPRI Datasheet - Page 67

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
Table 4–7. Resolution as a Function of M/N Ratio at 3072 Mbps on a Stratix IV GX Device
May 2011 Altera Corporation
Notes to
(1)
(2)
Table 4–1 on page 4–12
“CPRI Receive Buffer Delay Calculation Example”
cpri_clkout period.
128
64
M
1
Table
4–7:
127
63
N
4
M/N Ratio Selection
As your selected M/N ratio approaches 1, the accuracy provided by the use of the
clk_ex_delay clock increases.
resolutions they provide, for a CPRI IP core that runs at data rate 3072 Mbps and
targets a Stratix IV GX device.
CPRI Receive Buffer Delay Calculation Example
This section walks you through an example that shows you how to calculate the
frequency at which to run clk_ex_delay, and how to program and use the registers to
determine the delay through the CPRI Receive buffer.
For example, assume your CPRI IP core runs at data rate 3072 Mbps. In this case,
Table 4–1 on page 4–12
cpri_clkout cycle is 1/(76.80 MHz).
Refer to
your accuracy resolution requirements are satisfied by an M/N ratio of 128/127,
follow these steps:
1. Program the value N=127 in the rx_ex_delay field of the CPRI_EX_DELAY_CONFIG
2. Perform the following calculation to determine the clk_ex_delay frequency that
3. Read the value of the CPRI_EX_DELAY_STATUS register at offset 0x40
lists the cpri_clkout frequency for each CPRI data rate and device family.
register at offset 0x3C
supports your desired accuracy resolution:
clk_ex_delay period = (M/N) cpri_clkout period
Based on this calculation, the frequency of clk_ex_delay is
1/(13.123356 ns) = 76.20 MHz
The following steps assume that you run clk_ex_delay at this frequency.
page
If the rx_ex_buf_delay_valid field of the register is set to 1, the value in the
rx_ex_buf_delay field has been updated, and you can use it in the following
calculations. For this example, assume the value read from the rx_ex_buf_delay
field is 0x107D, which is decimal 4221.
Table 4–7
6–9).
cpri_clkout Period
(1/76.80 MHz)
13.02 ns
for the accuracy resolution provided by some sample M/N ratios. If
shows you how to calculate the clk_ex_delay clock period for a given M, N, and
shows that the cpri_clkout frequency is 76.80 MHz, so a
= (128/127) (1/(76.80 MHz))
= (128/127)(13.02083 ns)
= 13.123356 ns
(Table 6–19 on page
(1)
Table 4–7
clk_ex_delay Period
shows some example M/N ratios and the
13.12 ns
13.22 ns
3.25 ns
6–9).
(2)
CPRI MegaCore Function User Guide
Resolution
±3.25 ns
±100 ps
±200 ps
(Table 6–20 on
4–43