IP-CPRI Altera, IP-CPRI Datasheet - Page 43

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Physical Layer
May 2011 Altera Corporation
Descrambling
If the tx_prot_version field of the CPRI_TX_PROT_VER register
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the low-level CPRI receiver may need to descramble the incoming data, depending on
the values in the CPRI_RX_SCR_SEED register.
When the rx_scr_act_indication field of the CPRI_RX_SCR_SEED register
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according to the CPRI V4.1 Specification, using the seed in the rx_scr_seed field of
the CPRI_RX_SCR_SEED register. The seed value may be zero, indicating the incoming
data is not scrambled.
Performing Frame Synchronization
During frame synchronization, LOF is set to zero. LOS—the assertion of the gxb_los
signal—resets the frame synchronization state machine. Autorate negotiation occurs
in the first stage of frame synchronization, XACQ1.
synchronization state machine. If scrambling is configured in the CPRI link partner
(based on the value at Z.2.0 in the incoming CPRI communication), additional actions
and conditions apply on the state machine transitions, according to the CPRI V4.1
Specification. The CPRI IP core sets the values in the CPRI_RX_SCR_SEED register
according to these conditions.
6–11) holds the value 2, and the CPRI data rate is 4195.2 Mbps or 6144.0 Mbps,
6–12) is set, the low-level CPRI receiver descrambles the data words
Figure 4–10
CPRI MegaCore Function User Guide
(Table 6–25 on
shows the frame
(Table 6–27
4–19