IP-CPRI Altera, IP-CPRI Datasheet - Page 58

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–34
Auxiliary Interfaces
CPRI MegaCore Function User Guide
AUX Receiver Module
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The value 11 is reserved.
The CPRI_PRBS_STATUS register records the PRBS error detection status for each AxC
interface.
The CPRI auxiliary interfaces enable multihop routing applications and provide
timing reference information for transmitted and received frames. The AUX Receiver
and AUX transmitter interfaces are implemented as separate Avalon-ST interfaces.
The AUX transmitter receives data to be transmitted on the outgoing CPRI link, and
the AUX receiver transmits data received from the incoming CPRI link.
The AUX receiver module transmits data that the CPRI IP core received on the CPRI
link to the outgoing AUX Avalon-ST interface. In addition, it provides detailed
information about the current state in the Rx CPRI frame synchronization state
machine. This information is useful for custom user logic, including frame
synchronization across hops in multihop configurations.
The AUX interface receiver module provides the following data and synchronization
lines:
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The output synchronization signals are derived from the CPRI interface frame
synchronization machine. Their delay following the frame on the CPRI interface
reflects the quantified delay through the CPRI IP core. Refer to
page
information about the AUX receiver signals, refer to
01: Indicates an incremental counter sequence, starting at zero at the start of a
10 ms radio frame, and counting to 255 before rolling over. The counter value
appears in both halves of the 32-bit data word.
10: Indicates an inverted 2
halves of the 32-bit data word.
cpri_rx_sync_state—when set, indicates that Rx, HFN, and BFN
synchronization have been achieved in CPRI receiver frame synchronization
cpri_rx_start—asserted for the duration of the first basic frame following the
offset defined in the CPRI_START_OFFSET_RX register
cpri_rx_rfp and cpri_rx_hfp—synchronization pulses for start of 10 ms radio
frame and start of hyperframe
cpri_rx_bfn and cpri_rx_hfn—current radio frame and hyperframe numbers
cpri_rx_x—index number of the current basic frame in the current hyperframe
cpri_rx_seq—index number of the current 32-bit word in the current basic frame
cpri_rx_aux_data—outgoing data port for sending data and control words
received on the CPRI link out on the AUX interface
4–40. These signals are all fields in the aux_rx_status_data bus. For additional
23
– 1 PRBS sequence. Each pattern appears in both
Table 5–12 on page
Chapter 4: Functional Description
“Rx Path Delay” on
May 2011 Altera Corporation
Auxiliary Interfaces
5–11.