IP-CPRI Altera, IP-CPRI Datasheet - Page 105

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Software Interface
CPRI Interface Registers
Table 6–4. CPRI_INTR—Interrupt Control and Status—Offset: 0x0 (Part 2 of 2)
Table 6–5. CPRI_STATUS—CPRI Status—Offset: 0x4
Table 6–6. CPRI_CONFIG—CPRI Configuration—Offset: 0x8 (Part 1 of 2)
May 2011 Altera Corporation
intr_hw_reset_en
intr_en
RSRV
rx_rfp_hold
rx_freq_alarm_
hold
rx_state_hold
rx_los_hold
RSRV
los_lcv
RSRV
rx_bfn_state
rx_hfn_state
rx_state
rx_los
Note to
(1) This register field is a read-to-clear field. You must read the register twice to read the true value of the field after frame synchronization is
RSRV
tx_enable
achieved. If you observe this bit asserted during link initialization, read the register again after link initialization to confirm any errors.
Field
Table
Field
Field
6–5:
[31:12] UR0
[11]
[10]
[9]
[8]
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
Bits
[31:6] UR0
[5]
Bits
[1]
[0]
Bits
RC
RC
RC
RC
UR0
RO
UR0
RO
RO
RO
RO
Access
Access
RW
RW
RW
Reserved.
Radio frame pulse received. This bit is asserted every 10 ms.
CPRI receive clock is not synchronous with system clock
(cpri_clkout). This alarm is asserted each time mismatches are found
between the recovered CPRI receive clock and the system clock
cpri_clkout.
Hold rx_state.
Hold rx_los.
Reserved.
Loss of signal (LOS) detected. This alarm is asserted if excessive line
code violations (LCVs) are detected, based on two counters and two
programmable threshold values. The first counter counts up to the
expected amount of time to CPRI link synchronization, during which the
second counter does not count LCVs. The second counter counts LCVs
up to the threshold—the number of LCVs after which this alarm is
asserted. The CPRI_T_LCV register at offset 0x54 specifies the expected
amount of time to CPRI link synchronization, and the CPRI_N_LCV
register at offset 0x50 holds the threshold number of LCVs after which
this alarm is asserted.
Reserved.
Indicates BFN (Node B radio frame) synchronization has been achieved.
Indicates HFN synchronization has been achieved.
When set, indicates that Rx, HFN, and BFN synchronization have been
achieved in CPRI receiver frame synchronization.
Indicates either excessive 8B/10B violations (> 15) or incoming LOS
signal on dedicated line from SFP optical module (gxb_los signal).
Access
Reserved.
Enable transmission on CPRI link.
hw_reset interrupt enable. Controls whether a reset
request received over the CPRI link raises an interrupt on
the CPU IRQ line.
CPRI interface module interrupt enable.
The Ethernet and HDLC modules have separate interrupt
enable control bits.
(1)
(1)
(1)
Function
Function
Function
CPRI MegaCore Function User Guide
(1)
1’h0
1’h0
Default
Default
20'h0
1’h0
1’h0
1’h0
1’h0
2'h0
1’h0
1'h0
1’h0
1’h0
1’h0
1’h0
26'h0
1’h0
Default
6–3