IP-CPRI Altera, IP-CPRI Datasheet - Page 40

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–16
Physical Layer
CPRI MegaCore Function User Guide
Features
CPRI Link Reset Requests and Acknowledgements Based on hw_reset_assert Input Signal
The CPRI specification requires that the Z.130.0 reset bit must be detected by the CPRI
partner in four consecutive hyperframes before the CPRI partner confirms the reset
request. The reset generation request is in effect while hw_reset_assert remains
asserted, until the reset acknowledge control bit is detected on the incoming CPRI
link, as long as the reset_hw_en bit remains high.
To abort a reset request made by asserting the hw_reset_assert input signal, set the
reset_hw_en bit of the CPRI_HW_RESET register to 0.
A CPRI IP core in slave mode indicates that it detects a reset request sent in CPRI
communication by setting the reset_detect and reset_detect_hold bits of the
CPRI_HW_RESET register.
To acknowledge the reset request, the CPRI transmitter must send a reset
acknowledge on the CPRI link, by setting the Z.130.0 reset bit in ten consecutive
outgoing hyperframes. If the reset_hw_en bit of the CPRI_HW_RESET register is not set,
the CPRI transmitter sends a reset acknowledge only if the conditions described in
“CPRI Link Reset Requests and Acknowledgements Based on reset_gen_force
Register Field”
CPRI transmitter can send the reset acknowledge only if the application asserts the
hw_reset_assert signal. If the reset_out_en bit of the CPRI_HW_RESET register is set,
the CPRI IP core asserts the external hw_reset_req signal until the reset occurs. This
signal informs the application layer of the low-level reset request. If the reset_hw_en
bit is set and the hw_reset_req signal is asserted, you must set the hw_reset_assert
signal, to tell the CPRI transmitter to send a reset acknowledge on the CPRI link.
After it transmits the ten consecutive reset acknowledge bits, the CPRI transmitter
sets the reset_gen_done and reset_gen_done_hold bits.
For more information about the CPRI_HW_RESET register, refer to
page
Table 5–15 on page
After reset, your software must perform link synchronization and other initialization
tasks. For information about the required initialization sequence following CPRI IP
core reset, refer to
The physical layer of the CPRI protocol is also called layer 1. This layer controls the
electrical characteristics of the CPRI link, the time-division multiplexing of the
separate information flows in the protocol, and low-level signaling. The CPRI
interface module of the CPRI IP core incorporates Altera’s high-speed transceivers to
implement Layer 1. The transceivers are configured in deterministic latency mode,
supporting the extended delay measurement requirements of the CPRI specification.
This section describes features and blocks of the CPRI interface module.
shows a high-level block diagram of this module.
The physical layer has the following features:
■
Frame synchronization
6–5. For more information about the hw_reset_assert input signal, refer to
hold. If the reset_hw_en bit of the CPRI_HW_RESET register is set, the
Appendix A, Initialization
5–15.
Sequence.
Chapter 4: Functional Description
May 2011 Altera Corporation
Table 6–12 on
Figure 4–9
Physical Layer