IP-CPRI Altera, IP-CPRI Datasheet - Page 57

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
CPRI MAP Interface Module
May 2011 Altera Corporation
PRBS Generation and Validation
signal is asserted, assert the mapN_tx_resync signal to indicate that the samples on
mapN_tx_data can begin to fill the data words at the specified position in the CPRI
frame. Assertion of the mapN_tx_resync signal resets the write pointer of the current
antenna-carrier interface (mapN) Tx buffer to zero, so that the entire buffer is
available to receive the data from the data channel. The data on mapN_tx_data[31:0]
can safely be loaded in the mapN Tx buffer one cycle after the mapN_tx_resync signal
is asserted.
On the CPRI side of the mapN Tx buffer, the CPRI MAP transmitter interface reads
data from the mapN Tx buffer and sends it to the CPRI transmitter interface. The
offset programmed in the CPRI_MAP_OFFSET_TX register tells the CPRI MAP
transmitter interface when to reset the read pointer of the mapN Tx buffer and start
transferring data from the buffer to the CPRI transmitter interface. The K counter is
reset to zero at the same time, so that it advances from zero with the transfer of the
data to the CPRI transmitter interface, tracking the packing of the AxC container block
contents into the CPRI frame.
Because the mapN Tx buffer should not be read before it is written, the offset specified
in the CPRI_START_OFFSET_TX register must precede the offset specified in the
CPRI_MAP_OFFSET_TX register. The CPRI IP core informs you of buffer overflow and
underflow (in the CPRI_IQ_TX_BUF_STATUS register described in
page 6–18
Table 5–11 on page
recommends that you implement a separate tracking protocol to ensure you do not
overflow or underflow the mapN Tx buffer.
You set the values in the CPRI_START_OFFSET_TX and CPRI_MAP_OFFSET_TX registers to
provide the correct timing to compensate for delays through the CPRI IP core. For
information about delays in the Tx path through the IP core, refer to
on page
The delay through each mapN Tx buffer depends on whether the AxC data
communication is programmed in FIFO mode or in synchronous buffer mode. In
FIFO mode, the delay through the mapN Tx buffer depends on your programmed
threshold value and the application. The data is not read from the mapN Tx buffer
until the buffer threshold is reached, so the delay in the buffer depends on the fill
level. In synchronous buffer mode, because programmed offsets control the mapN Tx
buffer pointers, the delay can be quantified. In synchronous buffer mode, this delay is
one cycle if the sample rate is a multiple of 3.84 MHz, and two cycles otherwise.
The CPRI IP core supports generation and validation of several predetermined
pseudo-random binary sequences (PRBS) for antenna-carrier interface testing. The
value in the prbs_mode field of the CPRI_PRBS_CONFIG register specifies whether the
CPRI MAP interface module is in data mode or in internal loopback mode, and the
generated pattern for loopback mode. The value applies to all AxC interfaces. The
following prbs_mode values are available:
■
00: Indicates that data samples, and not a PRBS test pattern, are expected on the
AxC interfaces. This value indicates the CPRI MAP interface module is not in
internal loopback testing mode.
4–45.
and as reported in the mapN_tx_status_data output vector described in
5–9), but it does not prevent them from occurring. Altera
CPRI MegaCore Function User Guide
Table 6–47 on
“Tx Path Delay”
4–33