IP-CPRI Altera, IP-CPRI Datasheet - Page 81

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Data Link Layer for Slow Control and Management Channel (HDLC)
Data Link Layer for Slow Control and Management Channel (HDLC)
May 2011 Altera Corporation
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Software can set the ETH_RX_CONTROL rx_discard bit to abort the current received
packet. The Ethernet receiver ensures that following read from the Ethernet Rx buffer
is a start-of-packet word.
Ethernet Data Transfer
The next ready data word is available in the ETH_RX_DATA and ETH_RX_DATA_WAIT
registers. If no Ethernet data word is ready, reading from the ETH_RX_DATA_WAIT
register inserts wait states in the Ethernet channel. If no Ethernet data word is ready,
reading from the ETH_RX_DATA register causes the rx_abort bit to be set. The CPU
interface receiver module reads the Ethernet packet data one word at a time from one
of these registers.
If you turn on the Include MAC block parameter, your CPRI IP core includes an
internal HDLC block. If you turn off this parameter, an MII-like interface is available
for you to connect to your own external Ethernet MAC. In that case, the internal
HDLC block is not available and your application cannot access the HDLC registers.
If the internal HDLC block is turned off, attempts to access these registers read zeroes
and do not write successfully, as for a reserved register address.
In the CPRI IP core, the High-Level Data Link Control (HDLC), or slow data link
layer, passes HDLC data between the CPU interface and the CPRI receiver and
transmitter interfaces to the CPRI link. The CPRI specification dictates that the HDLC
channel rate is specified in the three lowest bits of control byte Z.66.0. The value
3’b000 indicates that no HDLC channel is supported in the current hyperframe.
Table 4–11
Table 4–11. HDLC Channel Bit Rates (Part 1 of 2)
The ETH_RX_STATUS rx_eop bit indicates that the next ready data word contains
the end-of-packet byte.
The ETH_RX_STATUS rx_length field indicates the number of valid bytes in the
end-of-packet word.
The ETH_RX_STATUS rx_abort bit indicates that the current received packet is
aborted.
The ETH_RX_STATUS rx_ready_block bit indicates that the next block of packet
data is ready to be read and does not contain the end-of-packet byte.
The ETH_RX_STATUS rx_ready_end bit indicates that the end-of-packet byte is
ready in the Ethernet Rx buffer.
Value in Z.66.0.0[2:0]
shows the possible rate configurations.
000
001
010
011
100
101
HDLC Bit Rate
(Kbps)
1920
2400
240
480
960
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CPRI MegaCore Function User Guide
Minimum CPRI Line Rate
(Mbps)
1228.8
2457.6
3072.0
614.4
614.4
614.4
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