XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 79

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.5.2 RAM Mapping
INITRM — Initialization of Internal RAM Position Register
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
RAM15
Bit 7
0
RAM14
6
0
MMSWAI — Memory Mapping Interface Stop in Wait Control
The MC68HC912D60A has 2K byte of fully static RAM that is used for
storing instructions, variables, and temporary data during program
execution. After reset, RAM addressing begins at location $0000 but can
be assigned to any 2K byte boundary within the standard 64K byte
address space. Mapping of internal RAM is controlled by five bits in the
INITRM register.
After reset, the first 512 bytes of RAM have their access inhibited by the
presence of the register address space. After initial MCU configuration,
it is recommended to map the register space at location $0800.
RAM[15:11] — Internal RAM map position
This bit controls access to the memory mapping interface when in
Wait mode.
Normal modes: write anytime; special modes: write never. Read
anytime.
0 = Memory mapping interface continues to function during Wait
mode.
1 = Memory mapping interface access is shut down during Wait
mode.
These bits specify the upper five bits of the 16-bit RAM address.
Normal modes: write once; special modes: write anytime. Read
anytime.
Operating Modes and Resource Mapping
RAM13
5
0
RAM12
4
0
RAM11
3
0
Operating Modes and Resource Mapping
2
0
0
1
0
0
Internal Resource Mapping
Bit 0
0
0
Technical Data
$0010
79

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