XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 450

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Glossary
cycle time — The period of the operating frequency: t
D — See “accumulators (A and B or D).”
decimal number system — Base 10 numbering system that uses the digits zero through nine.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
ECT — See “enhanced capture timer.”
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can
enhanced capture timer (ECT) — The HC12 Enhanced Capture Timer module has the features
exception — An event such as an interrupt or a reset that stops the sequential execution of the
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
full-duplex transmission — Communication on a channel in which data can be sent and
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing
Technical Data
450
usually represented by a percentage.
memory that can be electrically erased and reprogrammed.
be erased by exposure to an ultraviolet light source and then reprogrammed.
of the HC12 Standard Timer module enhanced by additional features in order to enlarge
the field of applications.
instructions in the main program.
over to zero and begins counting again.
received simultaneously.
through F.
modes, the CPU uses the contents of IX or IY to determine the effective address of the
operand. IX and IY can also serve as a temporary data storage locations.
Glossary
CYC
= 1/f
OP
.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor