XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 256

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Capture Timer
DDRT — Data Direction Register for Timer Port
PBCTL — 16-Bit Pulse Accumulator B Control Register
Technical Data
256
RESET:
RESET:
DDT7
BIT 7
BIT 7
0
0
0
DDT6
PBEN
6
0
6
0
Read: any time
Write: any time
PBEN — Pulse Accumulator B System Enable
Read or write any time.
The timer forces the I/O state to be an output for each timer port line
associated with an enabled output compare. In these cases the data
direction bits will not be changed, but have no effect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of
a pin when the associated timer output compare is disabled. Input
captures do not override the DDRT settings.
16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit
pulse accumulators PAC1 and PAC0.
When PBEN is set, the PACB is enabled. The PACB shares the input
pin with IC0.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output.
0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and
DDT5
5
0
5
0
0
PAC0 can be enabled when their related enable bits in
ICPACR ($A8) are set.
Enhanced Capture Timer
DDT4
4
0
4
0
0
DDT3
3
0
3
0
0
DDT2
2
0
2
0
0
PBOVI
DDT1
MC68HC912D60A — Rev. 3.1
1
0
1
0
Freescale Semiconductor
DDT0
BIT 0
BIT 0
0
0
0
$00AF
$00B0