XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 264

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Multiple Serial Interface
15.3 Block diagram
15.4 Serial Communication Interface (SCI)
Technical Data
264
MSI
Figure 15-1. Multiple Serial Interface Block Diagram
Two serial communication interfaces are available on the
MC68HC912D60A. These are NRZ format (one start, eight or nine data,
and one stop bit) asynchronous communication systems with
independent internal baud rate generation circuitry and SCI transmitters
and receivers. They can be configured for eight or nine data bits (one of
which may be designated as a parity bit, odd or even). If enabled, parity
is generated in hardware for transmitted and received data. Receiver
parity errors are flagged in hardware. The baud rate generator is based
on a modulus counter, allowing flexibility in choosing baud rates. There
is a receiver wake-up feature, an idle line detect feature, a loop-back
mode, and various error detection features. Two port pins for each SCI
provide the external interface for the transmitted data (TXD) and the
received data (RXD).
For a faster wake-up out of WAIT mode by a received SCI message,
both SCI have the capability of sending a receiver interrupt, if enabled,
when RAF (receiver active flag) is set. For compatibility with other
M68HC12 products, this feature is active only in WAIT mode and is
disabled when VDDPLL supply is at V
SCI0
SCI1
SPI
Multiple Serial Interface
MOSI/MOMI
MISO/SISO
CS/SS
RxD0
RxD1
TxD0
TxD1
SCK
SS
level.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7