XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 356

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Analog-to-Digital Converter
18.6.2 WAIT Mode
18.6.3 Background Debug (ATD FREEZE) Mode
18.6.4 Module Reset
Technical Data
356
If the ASWAI control bit in ATDCTL2 is set, then the ATD responds to
WAIT mode. If the ASWAI control bit is clear, then the ATD ignores the
WAIT signal. The ATD response to the wait mode is to power down the
module. In this mode, the MCU does not have access to the control,
status or result registers.
When debugging an application, it is useful to have the ATD pause when
a breakpoint is encountered. To accommodate this, there are two
FREEZE bits in the ATDCTL3 register used to select one of three
responses:
Control and timing logic is static allowing the register contents and timing
position to be remembered indefinitely. The analog electronics remains
powered up; however, internal leakage may compromise the accuracy
of a frozen conversion depending on the length of the freeze period.
When the BDM signal is negated clock activity resumes.
Access to the ATD register file is possible during the ‘frozen’ period.
The ATD module is reset on two different events.
The single difference between the two events is that the RST bit event
does not reset the ADPU bit to its reset state value - i.e. the module is
not reset into a powered down state and will be returned to an idle state.
1. The ATD module may ignore the freeze request.
2. It may respond to the freeze request by finishing the current
3. It may respond by immediately ‘freezing’.
1. In the case of a system reset.
2. If the RST bit in the ATDTEST register is activated.
conversion and ‘freezing’ before starting the next sample period.
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor

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