XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 53

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.1 Port A
3.6.2 Port B
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
which can be read and written at any time, and, with the exception of port
AD0, port AD1 (available only in 112TQFP), PE[1:0], RxCAN and
TxCAN, a data direction register which controls the direction of each pin.
After reset all general purpose I/O pins are configured as input.
Port A pins are used for address and data in expanded modes. In single
chip modes, the pins can be used as I/O. The port data register is not in
the address map during expanded and peripheral mode operation.
When it is in the map, port A can be read or written at anytime.
Register DDRA determines whether each port A pin is an input or output.
DDRA is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRA makes the corresponding bit in port A
an output; clearing a bit in DDRA makes the corresponding bit in port A
an input. The default reset state of DDRA is all zeros.
When the PUPA bit in the PUCR register is set, all port A input pins are
pulled-up internally by an active pull-up device. This bit has no effect if
the port is being used in expanded modes as the pull-ups are inactive.
Setting the RDPA bit in register RDRIV causes all port A outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to
Input/Output.
Port B pins are used for address and data in expanded modes. In single
chip modes, the pins can be used as I/O. The port data register is not in
the address map during expanded and peripheral mode operation.
When it is in the map, port B can be read or written at anytime.
Register DDRB determines whether each port B pin is an input or output.
DDRB is not in the address map during expanded and peripheral mode
operation. Setting a bit in DDRB makes the corresponding bit in port B
an output; clearing a bit in DDRB makes the corresponding bit in port B
an input. The default reset state of DDRB is all zeros.
Pinout and Signal Descriptions
Pinout and Signal Descriptions
Bus Control and
Technical Data
Port Signals
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