XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 127

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.7.5 Central Processing Unit
9.7.6 Memory
9.7.7 Other Resources
9.8 Register Stacking
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
If the MCU comes out of reset in an expanded mode, port A and port B
are used for the address/data bus, and port E pins are normally used to
control the external bus (operation of port E pins can be affected by the
PEAR register). Out of reset, port G, port H, port P, port S, port T, port
CAN[7:2], port AD0 and port AD1 are all configured as general-purpose
inputs.
After reset, the CPU fetches a vector from the appropriate address, then
begins executing instructions. The stack pointer and other CPU registers
are indeterminate immediately after reset. The CCR X and I interrupt
mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
After reset, the internal register block is located from $0000 to $01FF,
RAM is at $0000 to $07FF, and EEPROM is located at $0C00 to $0FFF.
In single chip mode the two Flash EEPROM modules are located from
$1000 to $7FFF and $8000 to $FFFF.
The enhanced capture timer (ECT), pulse width modulation timer
(PWM), serial communications interfaces (SCI0 and SCI1), serial
peripheral interface (SPI), Scalable CAN (MSCAN) and analog-to-digital
converters (ATD0 and ATD1) are off after reset.
Once enabled, an interrupt request can be recognized at any time after
the I bit in the CCR is cleared. When an interrupt service request is
recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles
Resets and Interrupts
Resets and Interrupts
Register Stacking
Technical Data
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