XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 237

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TQCR — Reserved
TCTL1 — Timer Control Register 1
TCTL2 — Timer Control Register 2
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
RESET:
RESET:
Bit 7
OM3
OM7
Bit 7
Bit 7
NOTE:
0
0
0
OL3
OL7
6
0
6
0
6
0
Read or write anytime.
OMn — Output Mode
OLn — Output Level
To enable output action by OMn and OLn bits on the timer port, the
corresponding bit in OC7M should be cleared.
These eight pairs of control bits are encoded to specify the output
action to be taken as a result of a successful OCn compare. When
either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
OM6
OM2
5
0
5
0
5
0
MCCNT register ($B6, $B7) clears the MCZF flag in the
MCFLG register ($A7). This has the advantage of eliminating
software overhead in a separate clear sequence. Extra care is
required to avoid accidental flag clearing due to unintended
accesses.
Enhanced Capture Timer
OL6
OL2
4
0
4
0
4
0
OM5
OM1
3
0
3
0
3
0
OL5
OL1
2
0
2
2
0
0
OM0
OM4
1
0
1
0
1
0
Enhanced Capture Timer
Bit 0
Bit 0
Bit 0
OL0
OL4
0
0
0
Timer Registers
Technical Data
$0087
$0088
$0089
237

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