XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 55

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.4 Port G
3.6.5 Port H
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Port G pins are used for key wake-ups that can be used with the pins
configured as inputs or outputs. The key wake-ups are triggered with a
falling edge signal (KWPG). An interrupt is generated if the
corresponding bit is enabled (KWIEG). If any of the interrupts is not
enabled, the corresponding pin can be used as a general purpose I/O
pin. Refer to
Register DDRG determines pin direction of port G when used for
general-purpose I/O. When DDRG bits are set, the corresponding pin is
configured for output. On reset the DDRG bits are cleared and the
corresponding pin is configured for input.
Port PGUPD determines what type of resistive load is used for port G
input pins when PUPG bit is set in the PUCR register. When PGUPD pin
is low, it loads a pull-down in all port G input pins. When PGUPD pin is
high, it loads a pull-up in all port G input pins.
In 80-pin version, the PGUPD is connected internally to VDD. The PG4
will have a pull-up. All port G pins should either be defined as outputs or
have their pull-ups enabled.
Setting the RDPG bit in register RDRIV causes all port G outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to
Input/Output.
Port H pins are used for key wake-ups that can be used with the pins
configured as inputs or outputs. The key wake-ups are triggered with a
falling edge signal (KWPH). An interrupt is generated if the
corresponding bit is enabled (KWIEH). If any of the interrupts is not
enabled, the corresponding pin can be used as a general purpose I/O
pin. Refer to
Register DDRH determines pin direction of Port H when used for
general-purpose I/O. When DDRH bits are set, the corresponding pin is
Pinout and Signal Descriptions
I/O Ports with Key
I/O Ports with Key
Wake-up.
Wake-up.
Pinout and Signal Descriptions
Bus Control and
Technical Data
Port Signals
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